af3dc4a7ca
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
147 lines
6.2 KiB
C
147 lines
6.2 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2005 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef ARM_AT91_AT91_PMCREG_H
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#define ARM_AT91_AT91_PMCREG_H
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/* Registers */
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#define PMC_SCER 0x00 /* System Clock Enable Register */
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#define PMC_SCDR 0x04 /* System Clock Disable Register */
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#define PMC_SCSR 0x08 /* System Clock Status Register */
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/* 0x0c reserved */
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#define PMC_PCER 0x10 /* Peripheral Clock Enable Register */
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#define PMC_PCDR 0x14 /* Peripheral Clock Disable Register */
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#define PMC_PCSR 0x18 /* Peripheral Clock Status Register */
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#define CKGR_UCKR 0x1c /* UTMI Clock Configuration Register */
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#define CKGR_MOR 0x20 /* Main Oscillator Register */
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#define CKGR_MCFR 0x24 /* Main Clock Frequency Register */
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#define CKGR_PLLAR 0x28 /* PLL A Register */
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#define CKGR_PLLBR 0x2c /* PLL B Register */
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#define PMC_MCKR 0x30 /* Master Clock Register */
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/* 0x34 reserved */
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#define PMC_USB 0x38 /* USB Clock Register */
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/* 0x3c reserved */
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#define PMC_PCK0 0x40 /* Programmable Clock 0 Register */
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#define PMC_PCK1 0x44 /* Programmable Clock 1 Register */
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#define PMC_PCK2 0x48 /* Programmable Clock 2 Register */
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#define PMC_PCK3 0x4c /* Programmable Clock 3 Register */
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/* 0x50 reserved */
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/* 0x54 reserved */
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/* 0x58 reserved */
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/* 0x5c reserved */
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#define PMC_IER 0x60 /* Interrupt Enable Register */
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#define PMC_IDR 0x64 /* Interrupt Disable Register */
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#define PMC_SR 0x68 /* Status Register */
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#define PMC_IMR 0x6c /* Interrupt Mask Register */
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/* 0x70 reserved */
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/* 0x74 reserved */
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/* 0x78 reserved */
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/* 0x7c reserved */
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#define PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */
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/* PMC System Clock Enable Register */
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/* PMC System Clock Disable Register */
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/* PMC System Clock StatusRegister */
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#define PMC_SCER_PCK (1UL << 0) /* PCK: Processor Clock Enable */
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#define PMC_SCER_UDP (1UL << 1) /* UDP: USB Device Port Clock Enable */
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#define PMC_SCER_MCKUDP (1UL << 2) /* MCKUDP: Master disable susp/res */
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#define PMC_SCER_UHP (1UL << 4) /* UHP: USB Host Port Clock Enable */
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#define PMC_SCER_PCK0 (1UL << 8) /* PCK0: Programmable Clock out en */
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#define PMC_SCER_PCK1 (1UL << 9) /* PCK1: Programmable Clock out en */
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#define PMC_SCER_PCK2 (1UL << 10) /* PCK2: Programmable Clock out en */
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#define PMC_SCER_PCK3 (1UL << 11) /* PCK3: Programmable Clock out en */
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#define PMC_SCER_UHP_SAM9 (1UL << 6) /* UHP: USB Host Port Clock Enable */
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#define PMC_SCER_UDP_SAM9 (1UL << 7) /* UDP: USB Device Port Clock Enable */
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/* PMC Peripheral Clock Enable Register */
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/* PMC Peripheral Clock Disable Register */
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/* PMC Peripheral Clock Status Register */
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/* Each bit here is 1 << peripheral number to enable/disable/status */
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/* PMC UTMI Clock Configuration Register */
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#define CKGR_UCKR_BIASEN (1UL << 24)
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#define CKGR_UCKR_UPLLEN (1UL << 16)
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/* PMC Clock Generator Main Oscillator Register */
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#define CKGR_MOR_MOSCEN (1UL << 0) /* MOSCEN: Main Oscillator Enable */
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#define CKGR_MOR_OSCBYPASS (1UL << 1) /* Oscillator Bypass */
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#define CKGR_MOR_OSCOUNT(x) (x << 8) /* Main Oscillator Start-up Time */
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/* PMC Clock Generator Main Clock Frequency Register */
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#define CKGR_MCFR_MAINRDY (1UL << 16) /* Main Clock Ready */
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#define CKGR_MCFR_MAINF_MASK 0xfffful /* Main Clock Frequency */
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/* PMC Clock Generator Master Clock Register */
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#define PMC_MCKR_PDIV (1 << 12) /* SAM9G20 Only */
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#define PMC_MCKR_PLLADIV2 (1 << 12) /* SAM9G45 Only */
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#define PMC_MCKR_CSS_MASK (3 << 0)
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#define PMC_MCKR_MDIV_MASK (3 << 8)
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#define PMC_MCKR_PRES_MASK (7 << 2)
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/* PMC USB Clock Register */
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#define PMC_USB_USBDIV(n) (((n) & 0x0F) << 8)
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#define PMC_USB_USBS (1 << 0)
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/* PMC Interrupt Enable Register */
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/* PMC Interrupt Disable Register */
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/* PMC Status Register */
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/* PMC Interrupt Mask Register */
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#define PMC_IER_MOSCS (1UL << 0) /* Main Oscillator Status */
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#define PMC_IER_LOCKA (1UL << 1) /* PLL A Locked */
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#define PMC_IER_LOCKB (1UL << 2) /* PLL B Locked */
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#define PMC_IER_MCKRDY (1UL << 3) /* Master Clock Status */
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#define PMC_IER_LOCKU (1UL << 6) /* UPLL Locked */
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#define PMC_IER_PCK0RDY (1UL << 8) /* Programmable Clock 0 Ready */
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#define PMC_IER_PCK1RDY (1UL << 9) /* Programmable Clock 1 Ready */
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#define PMC_IER_PCK2RDY (1UL << 10) /* Programmable Clock 2 Ready */
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#define PMC_IER_PCK3RDY (1UL << 11) /* Programmable Clock 3 Ready */
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/*
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* PLL input frequency spec sheet says it must be between 1MHz and 32MHz,
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* but it works down as low as 100kHz, a frequency necessary for some
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* output frequencies to work.
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*/
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#define PMC_PLL_MIN_IN_FREQ 100000
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#define PMC_PLL_MAX_IN_FREQ 32000000
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/*
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* PLL Max output frequency is 240MHz. The errata says 180MHz is the max
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* for some revisions of this part. Be more permissive and optimistic.
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*/
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#define PMC_PLL_MAX_OUT_FREQ 240000000
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#define PMC_PLL_MULT_MIN 2
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#define PMC_PLL_MULT_MAX 2048
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#define PMC_PLL_SHIFT_TOL 5 /* Allow errors 1 part in 32 */
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#define PMC_PLL_FAST_THRESH 155000000
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#endif /* ARM_AT91_AT91_PMCREG_H */
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