5c39c3ffa2
- correct setting of Auxiliary Control Register for MP mode - correct setting of Auxiliarty Debug registers - cleanup management of memory contains bootup code - early initialization of Coherency Fabric (MP and not-MP mode) - enable Snoop Filtering Obtained from: Semihalf
308 lines
8.1 KiB
C
308 lines
8.1 KiB
C
/*-
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* Copyright (c) 2011 Semihalf.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* From: FreeBSD: src/sys/arm/mv/kirkwood/sheevaplug.c,v 1.2 2010/06/13 13:28:53
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <machine/armreg.h>
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#include <arm/mv/mvwin.h>
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#include <arm/mv/mvreg.h>
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#include <arm/mv/mvvar.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <machine/fdt.h>
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#define CPU_FREQ_FIELD(sar) (((0x01 & (sar >> 52)) << 3) | \
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(0x07 & (sar >> 21)))
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#define FAB_FREQ_FIELD(sar) (((0x01 & (sar >> 51)) << 4) | \
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(0x0F & (sar >> 24)))
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static uint32_t count_l2clk(void);
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void armadaxp_l2_init(void);
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void armadaxp_init_coher_fabric(void);
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int platform_get_ncpus(void);
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#define ARMADAXP_L2_BASE (MV_BASE + 0x8000)
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#define ARMADAXP_L2_CTRL 0x100
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#define L2_ENABLE (1 << 0)
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#define ARMADAXP_L2_AUX_CTRL 0x104
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#define L2_WBWT_MODE_MASK (3 << 0)
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#define L2_WBWT_MODE_PAGE 0
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#define L2_WBWT_MODE_WB 1
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#define L2_WBWT_MODE_WT 2
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#define L2_REP_STRAT_MASK (3 << 27)
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#define L2_REP_STRAT_LSFR (1 << 27)
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#define L2_REP_STRAT_SEMIPLRU (3 << 27)
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#define ARMADAXP_L2_CNTR_CTRL 0x200
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#define ARMADAXP_L2_CNTR_CONF(x) (0x204 + (x) * 0xc)
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#define ARMADAXP_L2_CNTR2_VAL_LOW (0x208 + (x) * 0xc)
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#define ARMADAXP_L2_CNTR2_VAL_HI (0x20c + (x) * 0xc)
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#define ARMADAXP_L2_INT_CAUSE 0x220
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#define ARMADAXP_L2_SYNC_BARRIER 0x700
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#define ARMADAXP_L2_INV_WAY 0x778
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#define ARMADAXP_L2_CLEAN_WAY 0x7BC
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#define ARMADAXP_L2_FLUSH_PHYS 0x7F0
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#define ARMADAXP_L2_FLUSH_WAY 0x7FC
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#define MV_COHERENCY_FABRIC_BASE (MV_MBUS_BRIDGE_BASE + 0x200)
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#define COHER_FABRIC_CTRL 0x00
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#define COHER_FABRIC_CONF 0x04
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#define COHER_FABRIC_CFU 0x28
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#define COHER_FABRIC_CIB_CTRL 0x80
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/* XXX Make gpio driver optional and remove it */
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struct resource_spec mv_gpio_res[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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struct vco_freq_ratio {
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uint8_t vco_cpu; /* VCO to CLK0(CPU) clock ratio */
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uint8_t vco_l2c; /* VCO to NB(L2 cache) clock ratio */
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uint8_t vco_hcl; /* VCO to HCLK(DDR controller) clock ratio */
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uint8_t vco_ddr; /* VCO to DR(DDR memory) clock ratio */
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};
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static struct vco_freq_ratio freq_conf_table[] = {
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/*00*/ { 1, 1, 4, 2 },
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/*01*/ { 1, 2, 2, 2 },
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/*02*/ { 2, 2, 6, 3 },
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/*03*/ { 2, 2, 3, 3 },
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/*04*/ { 1, 2, 3, 3 },
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/*05*/ { 1, 2, 4, 2 },
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/*06*/ { 1, 1, 2, 2 },
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/*07*/ { 2, 3, 6, 6 },
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/*08*/ { 2, 3, 5, 5 },
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/*09*/ { 1, 2, 6, 3 },
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/*10*/ { 2, 4, 10, 5 },
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/*11*/ { 1, 3, 6, 6 },
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/*12*/ { 1, 2, 5, 5 },
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/*13*/ { 1, 3, 6, 3 },
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/*14*/ { 1, 2, 5, 5 },
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/*15*/ { 2, 2, 5, 5 },
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/*16*/ { 1, 1, 3, 3 },
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/*17*/ { 2, 5, 10, 10 },
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/*18*/ { 1, 3, 8, 4 },
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/*19*/ { 1, 1, 2, 1 },
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/*20*/ { 2, 3, 6, 3 },
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/*21*/ { 1, 2, 8, 4 },
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/*22*/ { 2, 5, 10, 5 }
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};
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static uint16_t cpu_clock_table[] = {
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1000, 1066, 1200, 1333, 1500, 1666, 1800, 2000, 600, 667, 800, 1600,
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2133, 2200, 2400 };
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uint32_t
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get_tclk(void)
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{
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uint32_t cputype;
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cputype = cpufunc_id();
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cputype &= CPU_ID_CPU_MASK;
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if (cputype == CPU_ID_MV88SV584X_V7)
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return (TCLK_250MHZ);
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else
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return (TCLK_200MHZ);
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}
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static uint32_t
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count_l2clk(void)
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{
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uint64_t sar_reg;
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uint32_t freq_vco, freq_l2clk;
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uint8_t sar_cpu_freq, sar_fab_freq, array_size;
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/* Get value of the SAR register and process it */
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sar_reg = get_sar_value();
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sar_cpu_freq = CPU_FREQ_FIELD(sar_reg);
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sar_fab_freq = FAB_FREQ_FIELD(sar_reg);
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/* Check if CPU frequency field has correct value */
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array_size = sizeof(cpu_clock_table) / sizeof(cpu_clock_table[0]);
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if (sar_cpu_freq >= array_size)
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panic("Reserved value in cpu frequency configuration field: "
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"%d", sar_cpu_freq);
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/* Check if fabric frequency field has correct value */
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array_size = sizeof(freq_conf_table) / sizeof(freq_conf_table[0]);
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if (sar_fab_freq >= array_size)
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panic("Reserved value in fabric frequency configuration field: "
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"%d", sar_fab_freq);
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/* Get CPU clock frequency */
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freq_vco = cpu_clock_table[sar_cpu_freq] *
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freq_conf_table[sar_fab_freq].vco_cpu;
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/* Get L2CLK clock frequency */
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freq_l2clk = freq_vco / freq_conf_table[sar_fab_freq].vco_l2c;
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/* Round L2CLK value to integer MHz */
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if (((freq_vco % freq_conf_table[sar_fab_freq].vco_l2c) * 10 /
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freq_conf_table[sar_fab_freq].vco_l2c) >= 5)
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freq_l2clk++;
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return (freq_l2clk * 1000000);
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}
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uint32_t
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get_l2clk(void)
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{
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static uint32_t l2clk_freq = 0;
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/* If get_l2clk is called first time get L2CLK value from register */
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if (l2clk_freq == 0)
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l2clk_freq = count_l2clk();
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return (l2clk_freq);
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}
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static uint32_t
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read_coher_fabric(uint32_t reg)
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{
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return (bus_space_read_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg));
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}
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static void
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write_coher_fabric(uint32_t reg, uint32_t val)
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{
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bus_space_write_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg, val);
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}
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int
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platform_get_ncpus(void)
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{
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#if !defined(SMP)
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return (1);
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#else
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return ((read_coher_fabric(COHER_FABRIC_CONF) & 0xf) + 1);
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#endif
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}
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void
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armadaxp_init_coher_fabric(void)
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{
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uint32_t val, cpus, mask;
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cpus = platform_get_ncpus();
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mask = (1 << cpus) - 1;
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val = read_coher_fabric(COHER_FABRIC_CTRL);
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val |= (mask << 24);
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write_coher_fabric(COHER_FABRIC_CTRL, val);
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val = read_coher_fabric(COHER_FABRIC_CONF);
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val |= (mask << 24);
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val |= (1 << 15);
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write_coher_fabric(COHER_FABRIC_CONF, val);
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}
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#define ALL_WAYS 0xffffffff
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/* L2 cache configuration registers */
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static uint32_t
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read_l2_cache(uint32_t reg)
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{
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return (bus_space_read_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg));
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}
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static void
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write_l2_cache(uint32_t reg, uint32_t val)
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{
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bus_space_write_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg, val);
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}
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static void
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armadaxp_l2_idcache_inv_all(void)
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{
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write_l2_cache(ARMADAXP_L2_INV_WAY, ALL_WAYS);
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}
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void
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armadaxp_l2_init(void)
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{
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u_int32_t reg;
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/* Set L2 policy */
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reg = read_l2_cache(ARMADAXP_L2_AUX_CTRL);
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reg &= ~(L2_WBWT_MODE_MASK);
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reg &= ~(L2_REP_STRAT_MASK);
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reg |= L2_REP_STRAT_SEMIPLRU;
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reg |= L2_WBWT_MODE_WT;
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write_l2_cache(ARMADAXP_L2_AUX_CTRL, reg);
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/* Invalidate l2 cache */
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armadaxp_l2_idcache_inv_all();
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/* Clear pending L2 interrupts */
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write_l2_cache(ARMADAXP_L2_INT_CAUSE, 0x1ff);
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/* Enable l2 cache */
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reg = read_l2_cache(ARMADAXP_L2_CTRL);
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write_l2_cache(ARMADAXP_L2_CTRL, reg | L2_ENABLE);
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/*
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* For debug purposes
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* Configure and enable counter
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*/
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write_l2_cache(ARMADAXP_L2_CNTR_CONF(0), 0xf0000 | (4 << 2));
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write_l2_cache(ARMADAXP_L2_CNTR_CONF(1), 0xf0000 | (2 << 2));
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write_l2_cache(ARMADAXP_L2_CNTR_CTRL, 0x303);
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/*
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* Enable Cache maintenance operation propagation in coherency fabric
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* Change point of coherency and point of unification to DRAM.
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*/
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reg = read_coher_fabric(COHER_FABRIC_CFU);
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reg |= (1 << 17) | (1 << 18);
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write_coher_fabric(COHER_FABRIC_CFU, reg);
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/* Coherent IO Bridge initialization */
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reg = read_coher_fabric(COHER_FABRIC_CIB_CTRL);
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reg &= ~(7 << 16);
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reg |= (7 << 16);
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write_coher_fabric(COHER_FABRIC_CIB_CTRL, reg);
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}
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