Marius Strobl 85083a8072 Retry up to 20 ms to enable bus power as at least with some Intel ... SDHCI/eMMC controllers the first attempt after a D3 to D0 transition, i. e. when the firmware has put the devices into D3 state before, can fail.		2017-07-02 19:13:01 +00:00
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fsl_sdhci.c	Use the newly added mpc85xx_get_system_clock()	2017-04-01 22:35:03 +00:00
sdhci_acpi.c	- Unlike as in the PCI case, when attached to ACPI, Intel Bay Trail	2017-05-14 21:33:01 +00:00
sdhci_fdt_gpio.c	Release all previously allocated resources.	2017-03-08 14:52:03 +00:00
sdhci_fdt_gpio.h	Add new helper routines for sdhci bridge drivers that use gpio pins for	2017-01-09 01:54:36 +00:00
sdhci_fdt.c	Add the Marvell SDHCI controller to the list of supported devices in	2017-05-16 05:10:15 +00:00
sdhci_if.m	o Add support for eMMC DDR bus speed mode at 52 MHz to sdhci(4) and	2017-03-19 23:27:17 +00:00
sdhci_pci.c	- Unlike as in the PCI case, when attached to ACPI, Intel Bay Trail	2017-05-14 21:33:01 +00:00
sdhci.c	Retry up to 20 ms to enable bus power as at least with some Intel	2017-07-02 19:13:01 +00:00
sdhci.h	Add a new SDHCI quirk, SDHCI_QUIRK_BROKEN_AUTO_STOP, to workaround	2017-05-09 19:01:57 +00:00