daf9197cff
will sometimes fail to initialize problem due to a lock contention with management hardware. However, in order to deliver that fix it was necessary to take a shared code update as a whole, and this required scattered changes in the core code to be compatible. The em driver now has VLAN HW support added as the igb driver had previously. MFC after: ASAP - in time for 7.1 RELEASE
557 lines
15 KiB
C
557 lines
15 KiB
C
/******************************************************************************
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Copyright (c) 2001-2008, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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/*
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* 82542 Gigabit Ethernet Controller
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*/
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#include "e1000_api.h"
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static s32 e1000_init_phy_params_82542(struct e1000_hw *hw);
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static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw);
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static s32 e1000_init_mac_params_82542(struct e1000_hw *hw);
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static s32 e1000_get_bus_info_82542(struct e1000_hw *hw);
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static s32 e1000_reset_hw_82542(struct e1000_hw *hw);
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static s32 e1000_init_hw_82542(struct e1000_hw *hw);
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static s32 e1000_setup_link_82542(struct e1000_hw *hw);
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static s32 e1000_led_on_82542(struct e1000_hw *hw);
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static s32 e1000_led_off_82542(struct e1000_hw *hw);
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static void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index);
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static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw);
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/**
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* e1000_init_phy_params_82542 - Init PHY func ptrs.
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* @hw: pointer to the HW structure
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**/
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static s32 e1000_init_phy_params_82542(struct e1000_hw *hw)
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{
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struct e1000_phy_info *phy = &hw->phy;
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s32 ret_val = E1000_SUCCESS;
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DEBUGFUNC("e1000_init_phy_params_82542");
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phy->type = e1000_phy_none;
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return ret_val;
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}
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/**
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* e1000_init_nvm_params_82542 - Init NVM func ptrs.
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* @hw: pointer to the HW structure
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**/
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static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw)
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{
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struct e1000_nvm_info *nvm = &hw->nvm;
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DEBUGFUNC("e1000_init_nvm_params_82542");
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nvm->address_bits = 6;
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nvm->delay_usec = 50;
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nvm->opcode_bits = 3;
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nvm->type = e1000_nvm_eeprom_microwire;
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nvm->word_size = 64;
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/* Function Pointers */
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nvm->ops.read = e1000_read_nvm_microwire;
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nvm->ops.release = e1000_stop_nvm;
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nvm->ops.write = e1000_write_nvm_microwire;
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nvm->ops.update = e1000_update_nvm_checksum_generic;
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nvm->ops.validate = e1000_validate_nvm_checksum_generic;
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return E1000_SUCCESS;
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}
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/**
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* e1000_init_mac_params_82542 - Init MAC func ptrs.
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* @hw: pointer to the HW structure
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**/
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static s32 e1000_init_mac_params_82542(struct e1000_hw *hw)
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{
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struct e1000_mac_info *mac = &hw->mac;
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DEBUGFUNC("e1000_init_mac_params_82542");
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/* Set media type */
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hw->phy.media_type = e1000_media_type_fiber;
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/* Set mta register count */
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mac->mta_reg_count = 128;
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/* Set rar entry count */
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mac->rar_entry_count = E1000_RAR_ENTRIES;
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/* Function pointers */
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/* bus type/speed/width */
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mac->ops.get_bus_info = e1000_get_bus_info_82542;
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/* function id */
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mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
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/* reset */
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mac->ops.reset_hw = e1000_reset_hw_82542;
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/* hw initialization */
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mac->ops.init_hw = e1000_init_hw_82542;
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/* link setup */
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mac->ops.setup_link = e1000_setup_link_82542;
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/* phy/fiber/serdes setup */
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mac->ops.setup_physical_interface = e1000_setup_fiber_serdes_link_generic;
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/* check for link */
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mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
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/* multicast address update */
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mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
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/* writing VFTA */
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mac->ops.write_vfta = e1000_write_vfta_generic;
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/* clearing VFTA */
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mac->ops.clear_vfta = e1000_clear_vfta_generic;
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/* setting MTA */
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mac->ops.mta_set = e1000_mta_set_generic;
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/* set RAR */
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mac->ops.rar_set = e1000_rar_set_82542;
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/* turn on/off LED */
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mac->ops.led_on = e1000_led_on_82542;
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mac->ops.led_off = e1000_led_off_82542;
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/* clear hardware counters */
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mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542;
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/* link info */
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mac->ops.get_link_up_info = e1000_get_speed_and_duplex_fiber_serdes_generic;
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return E1000_SUCCESS;
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}
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/**
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* e1000_init_function_pointers_82542 - Init func ptrs.
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* @hw: pointer to the HW structure
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*
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* Called to initialize all function pointers and parameters.
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**/
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void e1000_init_function_pointers_82542(struct e1000_hw *hw)
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{
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DEBUGFUNC("e1000_init_function_pointers_82542");
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hw->mac.ops.init_params = e1000_init_mac_params_82542;
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hw->nvm.ops.init_params = e1000_init_nvm_params_82542;
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hw->phy.ops.init_params = e1000_init_phy_params_82542;
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}
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/**
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* e1000_get_bus_info_82542 - Obtain bus information for adapter
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* @hw: pointer to the HW structure
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*
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* This will obtain information about the HW bus for which the
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* adapter is attached and stores it in the hw structure.
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**/
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static s32 e1000_get_bus_info_82542(struct e1000_hw *hw)
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{
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DEBUGFUNC("e1000_get_bus_info_82542");
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hw->bus.type = e1000_bus_type_pci;
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hw->bus.speed = e1000_bus_speed_unknown;
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hw->bus.width = e1000_bus_width_unknown;
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return E1000_SUCCESS;
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}
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/**
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* e1000_reset_hw_82542 - Reset hardware
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* @hw: pointer to the HW structure
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*
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* This resets the hardware into a known state.
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**/
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static s32 e1000_reset_hw_82542(struct e1000_hw *hw)
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{
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struct e1000_bus_info *bus = &hw->bus;
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s32 ret_val = E1000_SUCCESS;
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u32 ctrl, icr;
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DEBUGFUNC("e1000_reset_hw_82542");
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if (hw->revision_id == E1000_REVISION_2) {
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DEBUGOUT("Disabling MWI on 82542 rev 2\n");
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e1000_pci_clear_mwi(hw);
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}
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DEBUGOUT("Masking off all interrupts\n");
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E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
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E1000_WRITE_REG(hw, E1000_RCTL, 0);
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E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
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E1000_WRITE_FLUSH(hw);
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/*
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* Delay to allow any outstanding PCI transactions to complete before
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* resetting the device
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*/
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msec_delay(10);
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ctrl = E1000_READ_REG(hw, E1000_CTRL);
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DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n");
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E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
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hw->nvm.ops.reload(hw);
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msec_delay(2);
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E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
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icr = E1000_READ_REG(hw, E1000_ICR);
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if (hw->revision_id == E1000_REVISION_2) {
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if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
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e1000_pci_set_mwi(hw);
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}
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return ret_val;
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}
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/**
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* e1000_init_hw_82542 - Initialize hardware
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* @hw: pointer to the HW structure
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*
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* This inits the hardware readying it for operation.
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**/
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static s32 e1000_init_hw_82542(struct e1000_hw *hw)
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{
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struct e1000_mac_info *mac = &hw->mac;
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struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542;
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s32 ret_val = E1000_SUCCESS;
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u32 ctrl;
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u16 i;
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DEBUGFUNC("e1000_init_hw_82542");
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/* Disabling VLAN filtering */
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E1000_WRITE_REG(hw, E1000_VET, 0);
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mac->ops.clear_vfta(hw);
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/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
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if (hw->revision_id == E1000_REVISION_2) {
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DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
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e1000_pci_clear_mwi(hw);
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E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST);
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E1000_WRITE_FLUSH(hw);
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msec_delay(5);
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}
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/* Setup the receive address. */
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e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
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/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
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if (hw->revision_id == E1000_REVISION_2) {
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E1000_WRITE_REG(hw, E1000_RCTL, 0);
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E1000_WRITE_FLUSH(hw);
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msec_delay(1);
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if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
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e1000_pci_set_mwi(hw);
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}
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/* Zero out the Multicast HASH table */
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DEBUGOUT("Zeroing the MTA\n");
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for (i = 0; i < mac->mta_reg_count; i++)
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E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
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/*
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* Set the PCI priority bit correctly in the CTRL register. This
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* determines if the adapter gives priority to receives, or if it
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* gives equal priority to transmits and receives.
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*/
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if (dev_spec->dma_fairness) {
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ctrl = E1000_READ_REG(hw, E1000_CTRL);
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E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
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}
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/* Setup link and flow control */
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ret_val = e1000_setup_link_82542(hw);
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/*
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* Clear all of the statistics registers (clear on read). It is
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* important that we do this after we have tried to establish link
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* because the symbol error count will increment wildly if there
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* is no link.
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*/
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e1000_clear_hw_cntrs_82542(hw);
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return ret_val;
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}
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/**
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* e1000_setup_link_82542 - Setup flow control and link settings
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* @hw: pointer to the HW structure
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*
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* Determines which flow control settings to use, then configures flow
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* control. Calls the appropriate media-specific link configuration
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* function. Assuming the adapter has a valid link partner, a valid link
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* should be established. Assumes the hardware has previously been reset
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* and the transmitter and receiver are not enabled.
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**/
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static s32 e1000_setup_link_82542(struct e1000_hw *hw)
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{
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struct e1000_mac_info *mac = &hw->mac;
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s32 ret_val = E1000_SUCCESS;
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DEBUGFUNC("e1000_setup_link_82542");
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ret_val = e1000_set_default_fc_generic(hw);
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if (ret_val)
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goto out;
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hw->fc.requested_mode &= ~e1000_fc_tx_pause;
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if (mac->report_tx_early == 1)
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hw->fc.requested_mode &= ~e1000_fc_rx_pause;
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/*
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* Save off the requested flow control mode for use later. Depending
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* on the link partner's capabilities, we may or may not use this mode.
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*/
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hw->fc.current_mode = hw->fc.requested_mode;
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DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
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hw->fc.current_mode);
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/* Call the necessary subroutine to configure the link. */
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ret_val = mac->ops.setup_physical_interface(hw);
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if (ret_val)
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goto out;
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/*
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* Initialize the flow control address, type, and PAUSE timer
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* registers to their default values. This is done even if flow
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* control is disabled, because it does not hurt anything to
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* initialize these registers.
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*/
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DEBUGOUT("Initializing Flow Control address, type and timer regs\n");
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E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
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E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
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E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
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E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
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ret_val = e1000_set_fc_watermarks_generic(hw);
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out:
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return ret_val;
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}
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/**
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* e1000_led_on_82542 - Turn on SW controllable LED
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* @hw: pointer to the HW structure
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*
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* Turns the SW defined LED on.
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**/
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static s32 e1000_led_on_82542(struct e1000_hw *hw)
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{
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u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
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DEBUGFUNC("e1000_led_on_82542");
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ctrl |= E1000_CTRL_SWDPIN0;
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ctrl |= E1000_CTRL_SWDPIO0;
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E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
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return E1000_SUCCESS;
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}
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/**
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* e1000_led_off_82542 - Turn off SW controllable LED
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* @hw: pointer to the HW structure
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*
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* Turns the SW defined LED off.
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**/
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static s32 e1000_led_off_82542(struct e1000_hw *hw)
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{
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u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
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DEBUGFUNC("e1000_led_off_82542");
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ctrl &= ~E1000_CTRL_SWDPIN0;
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ctrl |= E1000_CTRL_SWDPIO0;
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E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
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return E1000_SUCCESS;
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}
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/**
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* e1000_rar_set_82542 - Set receive address register
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* @hw: pointer to the HW structure
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* @addr: pointer to the receive address
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* @index: receive address array register
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*
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* Sets the receive address array register at index to the address passed
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* in by addr.
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**/
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static void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index)
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{
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u32 rar_low, rar_high;
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DEBUGFUNC("e1000_rar_set_82542");
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/*
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* HW expects these in little endian so we reverse the byte order
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* from network order (big endian) to little endian
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*/
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rar_low = ((u32) addr[0] |
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((u32) addr[1] << 8) |
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((u32) addr[2] << 16) | ((u32) addr[3] << 24));
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rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
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/* If MAC address zero, no need to set the AV bit */
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if (rar_low || rar_high)
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rar_high |= E1000_RAH_AV;
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E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
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E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
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}
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/**
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* e1000_translate_register_82542 - Translate the proper register offset
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* @reg: e1000 register to be read
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*
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* Registers in 82542 are located in different offsets than other adapters
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* even though they function in the same manner. This function takes in
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* the name of the register to read and returns the correct offset for
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* 82542 silicon.
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**/
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u32 e1000_translate_register_82542(u32 reg)
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{
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/*
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* Some of the 82542 registers are located at different
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* offsets than they are in newer adapters.
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* Despite the difference in location, the registers
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* function in the same manner.
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*/
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switch (reg) {
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case E1000_RA:
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reg = 0x00040;
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break;
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case E1000_RDTR:
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reg = 0x00108;
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break;
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case E1000_RDBAL(0):
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reg = 0x00110;
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break;
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case E1000_RDBAH(0):
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reg = 0x00114;
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break;
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case E1000_RDLEN(0):
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reg = 0x00118;
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break;
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case E1000_RDH(0):
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reg = 0x00120;
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break;
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case E1000_RDT(0):
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reg = 0x00128;
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break;
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case E1000_RDBAL(1):
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reg = 0x00138;
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break;
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case E1000_RDBAH(1):
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reg = 0x0013C;
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break;
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case E1000_RDLEN(1):
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reg = 0x00140;
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break;
|
|
case E1000_RDH(1):
|
|
reg = 0x00148;
|
|
break;
|
|
case E1000_RDT(1):
|
|
reg = 0x00150;
|
|
break;
|
|
case E1000_FCRTH:
|
|
reg = 0x00160;
|
|
break;
|
|
case E1000_FCRTL:
|
|
reg = 0x00168;
|
|
break;
|
|
case E1000_MTA:
|
|
reg = 0x00200;
|
|
break;
|
|
case E1000_TDBAL(0):
|
|
reg = 0x00420;
|
|
break;
|
|
case E1000_TDBAH(0):
|
|
reg = 0x00424;
|
|
break;
|
|
case E1000_TDLEN(0):
|
|
reg = 0x00428;
|
|
break;
|
|
case E1000_TDH(0):
|
|
reg = 0x00430;
|
|
break;
|
|
case E1000_TDT(0):
|
|
reg = 0x00438;
|
|
break;
|
|
case E1000_TIDV:
|
|
reg = 0x00440;
|
|
break;
|
|
case E1000_VFTA:
|
|
reg = 0x00600;
|
|
break;
|
|
case E1000_TDFH:
|
|
reg = 0x08010;
|
|
break;
|
|
case E1000_TDFT:
|
|
reg = 0x08018;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return reg;
|
|
}
|
|
|
|
/**
|
|
* e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters
|
|
* @hw: pointer to the HW structure
|
|
*
|
|
* Clears the hardware counters by reading the counter registers.
|
|
**/
|
|
static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw)
|
|
{
|
|
DEBUGFUNC("e1000_clear_hw_cntrs_82542");
|
|
|
|
e1000_clear_hw_cntrs_base_generic(hw);
|
|
|
|
E1000_READ_REG(hw, E1000_PRC64);
|
|
E1000_READ_REG(hw, E1000_PRC127);
|
|
E1000_READ_REG(hw, E1000_PRC255);
|
|
E1000_READ_REG(hw, E1000_PRC511);
|
|
E1000_READ_REG(hw, E1000_PRC1023);
|
|
E1000_READ_REG(hw, E1000_PRC1522);
|
|
E1000_READ_REG(hw, E1000_PTC64);
|
|
E1000_READ_REG(hw, E1000_PTC127);
|
|
E1000_READ_REG(hw, E1000_PTC255);
|
|
E1000_READ_REG(hw, E1000_PTC511);
|
|
E1000_READ_REG(hw, E1000_PTC1023);
|
|
E1000_READ_REG(hw, E1000_PTC1522);
|
|
}
|