474 lines
10 KiB
C
474 lines
10 KiB
C
/*-
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* Copyright (c) 2000 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_IA64_CPU_H_
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#define _MACHINE_IA64_CPU_H_
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/*
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* Definition of PSR and IPSR bits.
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*/
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#define IA64_PSR_BE 0x0000000000000002
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#define IA64_PSR_UP 0x0000000000000004
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#define IA64_PSR_AC 0x0000000000000008
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#define IA64_PSR_MFL 0x0000000000000010
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#define IA64_PSR_MFH 0x0000000000000020
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#define IA64_PSR_IC 0x0000000000002000
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#define IA64_PSR_I 0x0000000000004000
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#define IA64_PSR_PK 0x0000000000008000
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#define IA64_PSR_DT 0x0000000000020000
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#define IA64_PSR_DFL 0x0000000000040000
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#define IA64_PSR_DFH 0x0000000000080000
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#define IA64_PSR_SP 0x0000000000100000
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#define IA64_PSR_PP 0x0000000000200000
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#define IA64_PSR_DI 0x0000000000400000
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#define IA64_PSR_SI 0x0000000000800000
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#define IA64_PSR_DB 0x0000000001000000
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#define IA64_PSR_LP 0x0000000002000000
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#define IA64_PSR_TB 0x0000000004000000
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#define IA64_PSR_RT 0x0000000008000000
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#define IA64_PSR_CPL 0x0000000300000000
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#define IA64_PSR_CPL_KERN 0x0000000000000000
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#define IA64_PSR_CPL_1 0x0000000100000000
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#define IA64_PSR_CPL_2 0x0000000200000000
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#define IA64_PSR_CPL_USER 0x0000000300000000
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#define IA64_PSR_IS 0x0000000400000000
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#define IA64_PSR_MC 0x0000000800000000
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#define IA64_PSR_IT 0x0000001000000000
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#define IA64_PSR_ID 0x0000002000000000
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#define IA64_PSR_DA 0x0000004000000000
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#define IA64_PSR_DD 0x0000008000000000
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#define IA64_PSR_SS 0x0000010000000000
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#define IA64_PSR_RI 0x0000060000000000
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#define IA64_PSR_RI_0 0x0000000000000000
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#define IA64_PSR_RI_1 0x0000020000000000
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#define IA64_PSR_RI_2 0x0000040000000000
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#define IA64_PSR_ED 0x0000080000000000
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#define IA64_PSR_BN 0x0000100000000000
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#define IA64_PSR_IA 0x0000200000000000
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/*
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* Definition of ISR bits.
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*/
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#define IA64_ISR_CODE 0x000000000000ffff
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#define IA64_ISR_VECTOR 0x0000000000ff0000
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#define IA64_ISR_X 0x0000000100000000
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#define IA64_ISR_W 0x0000000200000000
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#define IA64_ISR_R 0x0000000400000000
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#define IA64_ISR_NA 0x0000000800000000
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#define IA64_ISR_SP 0x0000001000000000
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#define IA64_ISR_RS 0x0000002000000000
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#define IA64_ISR_IR 0x0000004000000000
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#define IA64_ISR_NI 0x0000008000000000
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#define IA64_ISR_SO 0x0000010000000000
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#define IA64_ISR_EI 0x0000060000000000
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#define IA64_ISR_EI_0 0x0000000000000000
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#define IA64_ISR_EI_1 0x0000020000000000
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#define IA64_ISR_EI_2 0x0000040000000000
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#define IA64_ISR_ED 0x0000080000000000
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/*
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* Vector numbers for various ia64 interrupts.
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*/
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#define IA64_VEC_VHPT 0
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#define IA64_VEC_ITLB 1
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#define IA64_VEC_DTLB 2
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#define IA64_VEC_ALT_ITLB 3
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#define IA64_VEC_ALT_DTLB 4
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#define IA64_VEC_NESTED_DTLB 5
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#define IA64_VEC_IKEY_MISS 6
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#define IA64_VEC_DKEY_MISS 7
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#define IA64_VEC_DIRTY_BIT 8
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#define IA64_VEC_INST_ACCESS 9
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#define IA64_VEC_DATA_ACCESS 10
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#define IA64_VEC_BREAK 11
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#define IA64_VEC_EXT_INTR 12
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#define IA64_VEC_PAGE_NOT_PRESENT 20
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#define IA64_VEC_KEY_PERMISSION 21
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#define IA64_VEC_INST_ACCESS_RIGHTS 22
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#define IA64_VEC_DATA_ACCESS_RIGHTS 23
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#define IA64_VEC_GENERAL_EXCEPTION 24
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#define IA64_VEC_DISABLED_FP 25
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#define IA64_VEC_NAT_CONSUMPTION 26
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#define IA64_VEC_SPECULATION 27
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#define IA64_VEC_DEBUG 29
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#define IA64_VEC_UNALIGNED_REFERENCE 30
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#define IA64_VEC_UNSUPP_DATA_REFERENCE 31
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#define IA64_VEC_FLOATING_POINT_FAULT 32
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#define IA64_VEC_FLOATING_POINT_TRAP 33
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#define IA64_VEC_LOWER_PRIVILEGE_TRANSFER 34
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#define IA64_VEC_TAKEN_BRANCH_TRAP 35
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#define IA64_VEC_SINGLE_STEP_TRAP 36
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#define IA64_VEC_IA32_EXCEPTION 45
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#define IA64_VEC_IA32_INTERCEPT 46
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#define IA64_VEC_IA32_INTERRUPT 47
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/*
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* Manipulating region bits of an address.
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*/
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#define IA64_RR_BASE(n) (((u_int64_t) (n)) << 61)
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#define IA64_RR_MASK(x) ((x) & ((1L << 61) - 1))
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#define IA64_PHYS_TO_RR6(x) ((x) | IA64_RR_BASE(6))
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#define IA64_PHYS_TO_RR7(x) ((x) | IA64_RR_BASE(7))
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#ifndef LOCORE
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/*
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* Various special ia64 instructions.
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*/
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/*
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* Memory Fence.
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*/
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static __inline void
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ia64_mf(void)
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{
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__asm __volatile("mf");
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}
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static __inline void
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ia64_mf_a(void)
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{
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__asm __volatile("mf.a");
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}
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/*
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* Flush Cache.
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*/
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static __inline void
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ia64_fc(u_int64_t va)
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{
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__asm __volatile("fc %0" :: "r"(va));
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}
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/*
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* Calculate address in VHPT for va.
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*/
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static __inline u_int64_t
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ia64_thash(u_int64_t va)
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{
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u_int64_t result;
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__asm __volatile("thash %0=%1" : "=r" (result) : "r" (va));
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return result;
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}
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/*
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* Calculate VHPT tag for va.
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*/
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static __inline u_int64_t
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ia64_ttag(u_int64_t va)
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{
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u_int64_t result;
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__asm __volatile("ttag %0=%1" : "=r" (result) : "r" (va));
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return result;
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}
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/*
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* Convert virtual address to physical.
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*/
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static __inline u_int64_t
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ia64_tpa(u_int64_t va)
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{
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u_int64_t result;
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__asm __volatile("tpa %0=%1" : "=r" (result) : "r" (va));
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return result;
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}
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/*
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* Generate a ptc.e instruction.
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*/
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static __inline void
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ia64_ptc_e(u_int64_t v)
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{
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__asm __volatile("ptc.e %0;;" :: "r"(v));
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}
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/*
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* Generate a ptc.g instruction.
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*/
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static __inline void
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ia64_ptc_g(u_int64_t va, u_int64_t log2size)
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{
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__asm __volatile("ptc.g %0,%1;;" :: "r"(va), "r"(log2size));
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}
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/*
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* Generate a ptc.ga instruction.
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*/
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static __inline void
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ia64_ptc_ga(u_int64_t va, u_int64_t log2size)
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{
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__asm __volatile("ptc.ga %0,%1;;" :: "r"(va), "r"(log2size));
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}
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/*
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* Generate a ptc.l instruction.
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*/
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static __inline void
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ia64_ptc_l(u_int64_t va, u_int64_t log2size)
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{
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__asm __volatile("ptc.l %0,%1;;" :: "r"(va), "r"(log2size));
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}
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/*
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* Read the value of psr.
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*/
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static __inline u_int64_t
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ia64_get_psr(void)
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{
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u_int64_t result;
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__asm __volatile("mov %0=psr;;" : "=r" (result));
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return result;
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}
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/*
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* Read the value of ar.k0.
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*/
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static __inline u_int64_t
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ia64_get_k0(void)
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{
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u_int64_t result;
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__asm __volatile("mov %0=ar.k0" : "=r" (result));
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return result;
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}
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/*
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* Read the value of ar.k1.
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*/
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static __inline u_int64_t
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ia64_get_k1(void)
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{
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u_int64_t result;
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__asm __volatile("mov %0=ar.k1" : "=r" (result));
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return result;
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}
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/*
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* Read the value of ar.k2.
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*/
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static __inline u_int64_t
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ia64_get_k2(void)
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{
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u_int64_t result;
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__asm __volatile("mov %0=ar.k2" : "=r" (result));
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return result;
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}
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/*
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* Read the value of ar.k3.
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*/
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static __inline u_int64_t
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ia64_get_k3(void)
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{
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u_int64_t result;
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__asm __volatile("mov %0=ar.k3" : "=r" (result));
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return result;
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}
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/*
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* Read the value of ar.k4.
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*/
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static __inline u_int64_t
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ia64_get_k4(void)
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{
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u_int64_t result;
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__asm __volatile("mov %0=ar.k4" : "=r" (result));
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return result;
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}
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/*
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* Read the value of ar.k5.
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*/
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static __inline u_int64_t
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ia64_get_k5(void)
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{
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u_int64_t result;
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__asm __volatile("mov %0=ar.k5" : "=r" (result));
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return result;
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}
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/*
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* Read the value of ar.k6.
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*/
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static __inline u_int64_t
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ia64_get_k6(void)
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{
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u_int64_t result;
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__asm __volatile("mov %0=ar.k6" : "=r" (result));
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return result;
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}
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/*
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* Read the value of ar.k7.
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*/
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static __inline u_int64_t
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ia64_get_k7(void)
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{
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u_int64_t result;
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__asm __volatile("mov %0=ar.k7" : "=r" (result));
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return result;
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}
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/*
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* Write the value of ar.k0.
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*/
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static __inline void
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ia64_set_k0(u_int64_t v)
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{
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__asm __volatile("mov ar.k0=%0" :: "r" (v));
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}
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/*
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* Write the value of ar.k1.
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*/
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static __inline void
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ia64_set_k1(u_int64_t v)
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{
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__asm __volatile("mov ar.k1=%0" :: "r" (v));
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}
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/*
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* Write the value of ar.k2.
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*/
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static __inline void
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ia64_set_k2(u_int64_t v)
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{
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__asm __volatile("mov ar.k2=%0" :: "r" (v));
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}
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/*
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* Write the value of ar.k3.
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*/
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static __inline void
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ia64_set_k3(u_int64_t v)
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{
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__asm __volatile("mov ar.k3=%0" :: "r" (v));
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}
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/*
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* Write the value of ar.k4.
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*/
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static __inline void
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ia64_set_k4(u_int64_t v)
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{
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__asm __volatile("mov ar.k4=%0" :: "r" (v));
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}
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/*
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* Write the value of ar.k5.
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*/
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static __inline void
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ia64_set_k5(u_int64_t v)
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{
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__asm __volatile("mov ar.k5=%0" :: "r" (v));
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}
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/*
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* Write the value of ar.k6.
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*/
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static __inline void
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ia64_set_k6(u_int64_t v)
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{
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__asm __volatile("mov ar.k6=%0" :: "r" (v));
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}
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/*
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* Write the value of ar.k7.
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*/
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static __inline void
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ia64_set_k7(u_int64_t v)
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{
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__asm __volatile("mov ar.k7=%0" :: "r" (v));
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}
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/*
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* Read the value of ar.itc.
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*/
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static __inline u_int64_t
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ia64_get_itc(void)
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{
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u_int64_t result;
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__asm __volatile("mov %0=ar.itc" : "=r" (result));
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return result;
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}
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/*
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* Read the value of ar.itm.
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*/
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static __inline u_int64_t
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ia64_get_itm(void)
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{
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u_int64_t result;
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__asm __volatile("mov %0=cr.itm" : "=r" (result));
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return result;
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}
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/*
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* Write the value of ar.itm.
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*/
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static __inline void
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ia64_set_itm(u_int64_t v)
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{
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__asm __volatile("mov cr.itm=%0" :: "r" (v));
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}
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/*
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* Write the value of ar.itv.
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*/
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static __inline void
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ia64_set_itv(u_int64_t v)
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{
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__asm __volatile("mov cr.itv=%0" :: "r" (v));
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}
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/*
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* Write a region register.
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*/
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static __inline void
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ia64_set_rr(u_int64_t rrbase, u_int64_t v)
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{
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__asm __volatile("mov rr[%0]=%1" :: "r"(rrbase), "r"(v) : "memory");
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}
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/*
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* Read a CPUID register.
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*/
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static __inline u_int64_t
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ia64_get_cpuid(int i)
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{
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u_int64_t result;
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__asm __volatile("mov %0=cpuid[%1]"
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: "=r" (result) : "r"(i));
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return result;
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}
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#endif
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#endif /* _MACHINE_IA64_CPU_H_ */
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