127 lines
3.1 KiB
C
127 lines
3.1 KiB
C
/*-
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* SPDX-License-Identifier: ISC
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*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ah_devid.h"
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#ifdef AH_DEBUG
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#include "ah_desc.h" /* NB: for HAL_PHYERR* */
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#endif
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#include "ar5212/ar5212.h"
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#include "ar5212/ar5212reg.h"
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#include "ar5212/ar5212phy.h"
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#define AR_NUM_GPIO 6 /* 6 GPIO pins */
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#define AR_GPIOD_MASK 0x0000002F /* GPIO data reg r/w mask */
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/*
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* Configure GPIO Output lines
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*/
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HAL_BOOL
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ar5212GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)
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{
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HALASSERT(gpio < AR_NUM_GPIO);
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/*
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* NB: AR_GPIOCR_CR_A(pin) is all 1's so there's no need
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* to clear the field before or'ing in the new value.
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*/
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OS_REG_WRITE(ah, AR_GPIOCR,
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OS_REG_READ(ah, AR_GPIOCR) | AR_GPIOCR_CR_A(gpio));
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return AH_TRUE;
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}
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/*
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* Configure GPIO Input lines
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*/
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HAL_BOOL
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ar5212GpioCfgInput(struct ath_hal *ah, uint32_t gpio)
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{
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HALASSERT(gpio < AR_NUM_GPIO);
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OS_REG_WRITE(ah, AR_GPIOCR,
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(OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_CR_A(gpio))
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| AR_GPIOCR_CR_N(gpio));
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return AH_TRUE;
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}
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/*
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* Once configured for I/O - set output lines
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*/
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HAL_BOOL
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ar5212GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)
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{
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uint32_t reg;
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HALASSERT(gpio < AR_NUM_GPIO);
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reg = OS_REG_READ(ah, AR_GPIODO);
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reg &= ~(1 << gpio);
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reg |= (val&1) << gpio;
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OS_REG_WRITE(ah, AR_GPIODO, reg);
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return AH_TRUE;
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}
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/*
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* Once configured for I/O - get input lines
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*/
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uint32_t
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ar5212GpioGet(struct ath_hal *ah, uint32_t gpio)
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{
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if (gpio < AR_NUM_GPIO) {
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uint32_t val = OS_REG_READ(ah, AR_GPIODI);
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val = ((val & AR_GPIOD_MASK) >> gpio) & 0x1;
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return val;
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} else {
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return 0xffffffff;
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}
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}
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/*
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* Set the GPIO Interrupt
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*/
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void
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ar5212GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)
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{
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uint32_t val;
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/* XXX bounds check gpio */
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val = OS_REG_READ(ah, AR_GPIOCR);
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val &= ~(AR_GPIOCR_CR_A(gpio) |
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AR_GPIOCR_INT_MASK | AR_GPIOCR_INT_ENA | AR_GPIOCR_INT_SEL);
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val |= AR_GPIOCR_CR_N(gpio) | AR_GPIOCR_INT(gpio) | AR_GPIOCR_INT_ENA;
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if (ilevel)
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val |= AR_GPIOCR_INT_SELH; /* interrupt on pin high */
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else
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val |= AR_GPIOCR_INT_SELL; /* interrupt on pin low */
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/* Don't need to change anything for low level interrupt. */
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OS_REG_WRITE(ah, AR_GPIOCR, val);
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/* Change the interrupt mask. */
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(void) ar5212SetInterrupts(ah, AH5212(ah)->ah_maskReg | HAL_INT_GPIO);
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}
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