461 lines
13 KiB
C
461 lines
13 KiB
C
/*-
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* SPDX-License-Identifier: ISC
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*
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* Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
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* Copyright (c) 2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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/*
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* NB: Merlin and later have a simpler RF backend.
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*/
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#include "ah.h"
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#include "ah_internal.h"
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#include "ah_eeprom_v14.h"
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#include "ar9002/ar9280.h"
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#include "ar5416/ar5416reg.h"
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#include "ar5416/ar5416phy.h"
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#define N(a) (sizeof(a)/sizeof(a[0]))
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struct ar9280State {
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RF_HAL_FUNCS base; /* public state, must be first */
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uint16_t pcdacTable[1]; /* XXX */
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};
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#define AR9280(ah) ((struct ar9280State *) AH5212(ah)->ah_rfHal)
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static HAL_BOOL ar9280GetChannelMaxMinPower(struct ath_hal *,
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const struct ieee80211_channel *, int16_t *maxPow,int16_t *minPow);
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int16_t ar9280GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c);
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static void
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ar9280WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
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int writes)
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{
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(void) ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_bb_rfgain,
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freqIndex, writes);
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}
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/*
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* Take the MHz channel value and set the Channel value
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*
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* ASSUMES: Writes enabled to analog bus
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*
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* Actual Expression,
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*
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* For 2GHz channel,
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* Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
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* (freq_ref = 40MHz)
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*
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* For 5GHz channel,
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* Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
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* (freq_ref = 40MHz/(24>>amodeRefSel))
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*
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* For 5GHz channels which are 5MHz spaced,
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* Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
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* (freq_ref = 40MHz)
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*/
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static HAL_BOOL
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ar9280SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
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{
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uint16_t bMode, fracMode, aModeRefSel = 0;
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uint32_t freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
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CHAN_CENTERS centers;
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uint32_t refDivA = 24;
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uint8_t frac_n_5g;
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OS_MARK(ah, AH_MARK_SETCHANNEL, chan->ic_freq);
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ar5416GetChannelCenters(ah, chan, ¢ers);
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freq = centers.synth_center;
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reg32 = OS_REG_READ(ah, AR_PHY_SYNTH_CONTROL);
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reg32 &= 0xc0000000;
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if (ath_hal_eepromGet(ah, AR_EEP_FRAC_N_5G, &frac_n_5g) != HAL_OK)
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frac_n_5g = 0;
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if (freq < 4800) { /* 2 GHz, fractional mode */
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uint32_t txctl;
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bMode = 1;
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fracMode = 1;
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aModeRefSel = 0;
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channelSel = (freq * 0x10000)/15;
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txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
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if (freq == 2484) {
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/* Enable channel spreading for channel 14 */
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OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
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txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
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} else {
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OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
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txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
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}
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} else {
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bMode = 0;
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fracMode = 0;
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switch (frac_n_5g) {
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case 0:
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/*
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* Enable fractional mode for half/quarter rate
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* channels.
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*
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* This is from the Linux ath9k code, rather than
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* the Atheros HAL code.
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*/
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if (IEEE80211_IS_CHAN_QUARTER(chan) ||
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IEEE80211_IS_CHAN_HALF(chan))
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aModeRefSel = 0;
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else if ((freq % 20) == 0) {
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aModeRefSel = 3;
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} else if ((freq % 10) == 0) {
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aModeRefSel = 2;
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}
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if (aModeRefSel) break;
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case 1:
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default:
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aModeRefSel = 0;
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/* Enable 2G (fractional) mode for channels which are 5MHz spaced */
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/*
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* Workaround for talking on PSB non-5MHz channels;
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* the pre-Merlin chips only had a 2.5MHz channel
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* spacing so some channels aren't reachable.
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*
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* This interoperates on the quarter rate channels
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* with the AR5112 and later RF synths. Please note
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* that the synthesiser isn't able to completely
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* accurately represent these frequencies (as the
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* resolution in this reference is 2.5MHz) and thus
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* it will be slightly "off centre." This matches
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* the same slightly incorrect centre frequency
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* behaviour that the AR5112 and later channel
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* selection code has.
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*
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* This also interoperates with the AR5416
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* synthesiser modification for programming
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* fractional frequencies in 5GHz mode. However
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* that modification is also disabled by default.
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*
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* This is disabled because it hasn't been tested for
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* regulatory compliance and neither have the NICs
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* which would use it. So if you enable this code,
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* you must first ensure that you've re-certified the
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* NICs in question beforehand or you will be
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* violating your local regulatory rules and breaking
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* the law.
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*/
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#if 0
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if (freq % 5 == 0) {
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#endif
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/* Normal */
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fracMode = 1;
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refDivA = 1;
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channelSel = (freq * 0x8000)/15;
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#if 0
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} else {
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/* Offset by 500KHz */
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uint32_t f, ch, ch2;
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fracMode = 1;
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refDivA = 1;
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/* Calculate the "adjusted" frequency */
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f = freq - 2;
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ch = (((f - 4800) * 10) / 25) + 1;
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ch2 = ((ch * 25) / 5) + 9600;
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channelSel = (ch2 * 0x4000) / 15;
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//ath_hal_printf(ah,
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// "%s: freq=%d, ch=%d, ch2=%d, "
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// "channelSel=%d\n",
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// __func__, freq, ch, ch2, channelSel);
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}
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#endif
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/* RefDivA setting */
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OS_A_REG_RMW_FIELD(ah, AR_AN_SYNTH9,
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AR_AN_SYNTH9_REFDIVA, refDivA);
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}
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if (!fracMode) {
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ndiv = (freq * (refDivA >> aModeRefSel))/60;
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channelSel = ndiv & 0x1ff;
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channelFrac = (ndiv & 0xfffffe00) * 2;
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channelSel = (channelSel << 17) | channelFrac;
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}
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}
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reg32 = reg32 | (bMode << 29) | (fracMode << 28) |
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(aModeRefSel << 26) | (channelSel);
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OS_REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
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AH_PRIVATE(ah)->ah_curchan = chan;
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return AH_TRUE;
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}
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/*
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* Return a reference to the requested RF Bank.
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*/
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static uint32_t *
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ar9280GetRfBank(struct ath_hal *ah, int bank)
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{
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
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__func__, bank);
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return AH_NULL;
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}
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/*
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* Reads EEPROM header info from device structure and programs
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* all rf registers
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*/
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static HAL_BOOL
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ar9280SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,
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uint16_t modesIndex, uint16_t *rfXpdGain)
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{
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return AH_TRUE; /* nothing to do */
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}
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/*
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* Read the transmit power levels from the structures taken from EEPROM
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* Interpolate read transmit power values for this channel
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* Organize the transmit power values into a table for writing into the hardware
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*/
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static HAL_BOOL
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ar9280SetPowerTable(struct ath_hal *ah, int16_t *pPowerMin, int16_t *pPowerMax,
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const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
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{
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return AH_TRUE;
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}
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#if 0
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static int16_t
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ar9280GetMinPower(struct ath_hal *ah, EXPN_DATA_PER_CHANNEL_5112 *data)
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{
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int i, minIndex;
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int16_t minGain,minPwr,minPcdac,retVal;
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/* Assume NUM_POINTS_XPD0 > 0 */
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minGain = data->pDataPerXPD[0].xpd_gain;
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for (minIndex=0,i=1; i<NUM_XPD_PER_CHANNEL; i++) {
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if (data->pDataPerXPD[i].xpd_gain < minGain) {
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minIndex = i;
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minGain = data->pDataPerXPD[i].xpd_gain;
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}
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}
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minPwr = data->pDataPerXPD[minIndex].pwr_t4[0];
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minPcdac = data->pDataPerXPD[minIndex].pcdac[0];
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for (i=1; i<NUM_POINTS_XPD0; i++) {
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if (data->pDataPerXPD[minIndex].pwr_t4[i] < minPwr) {
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minPwr = data->pDataPerXPD[minIndex].pwr_t4[i];
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minPcdac = data->pDataPerXPD[minIndex].pcdac[i];
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}
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}
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retVal = minPwr - (minPcdac*2);
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return(retVal);
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}
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#endif
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static HAL_BOOL
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ar9280GetChannelMaxMinPower(struct ath_hal *ah,
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const struct ieee80211_channel *chan,
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int16_t *maxPow, int16_t *minPow)
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{
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#if 0
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struct ath_hal_5212 *ahp = AH5212(ah);
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int numChannels=0,i,last;
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int totalD, totalF,totalMin;
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EXPN_DATA_PER_CHANNEL_5112 *data=AH_NULL;
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EEPROM_POWER_EXPN_5112 *powerArray=AH_NULL;
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*maxPow = 0;
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if (IS_CHAN_A(chan)) {
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powerArray = ahp->ah_modePowerArray5112;
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data = powerArray[headerInfo11A].pDataPerChannel;
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numChannels = powerArray[headerInfo11A].numChannels;
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} else if (IS_CHAN_G(chan) || IS_CHAN_108G(chan)) {
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/* XXX - is this correct? Should we also use the same power for turbo G? */
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powerArray = ahp->ah_modePowerArray5112;
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data = powerArray[headerInfo11G].pDataPerChannel;
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numChannels = powerArray[headerInfo11G].numChannels;
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} else if (IS_CHAN_B(chan)) {
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powerArray = ahp->ah_modePowerArray5112;
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data = powerArray[headerInfo11B].pDataPerChannel;
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numChannels = powerArray[headerInfo11B].numChannels;
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} else {
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return (AH_TRUE);
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}
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/* Make sure the channel is in the range of the TP values
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* (freq piers)
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*/
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if ((numChannels < 1) ||
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(chan->channel < data[0].channelValue) ||
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(chan->channel > data[numChannels-1].channelValue))
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return(AH_FALSE);
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/* Linearly interpolate the power value now */
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for (last=0,i=0;
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(i<numChannels) && (chan->channel > data[i].channelValue);
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last=i++);
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totalD = data[i].channelValue - data[last].channelValue;
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if (totalD > 0) {
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totalF = data[i].maxPower_t4 - data[last].maxPower_t4;
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*maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + data[last].maxPower_t4*totalD)/totalD);
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totalMin = ar9280GetMinPower(ah,&data[i]) - ar9280GetMinPower(ah, &data[last]);
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*minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) + ar9280GetMinPower(ah, &data[last])*totalD)/totalD);
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return (AH_TRUE);
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} else {
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if (chan->channel == data[i].channelValue) {
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*maxPow = data[i].maxPower_t4;
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*minPow = ar9280GetMinPower(ah, &data[i]);
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return(AH_TRUE);
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} else
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return(AH_FALSE);
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}
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#else
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*maxPow = *minPow = 0;
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return AH_FALSE;
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#endif
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}
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/*
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* The ordering of nfarray is thus:
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*
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* nfarray[0]: Chain 0 ctl
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* nfarray[1]: Chain 1 ctl
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* nfarray[2]: Chain 2 ctl
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* nfarray[3]: Chain 0 ext
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* nfarray[4]: Chain 1 ext
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* nfarray[5]: Chain 2 ext
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*/
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static void
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ar9280GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])
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{
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int16_t nf;
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nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
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if (nf & 0x100)
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nf = 0 - ((nf ^ 0x1ff) + 1);
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HALDEBUG(ah, HAL_DEBUG_NFCAL,
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"NF calibrated [ctl] [chain 0] is %d\n", nf);
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nfarray[0] = nf;
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nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
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if (nf & 0x100)
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nf = 0 - ((nf ^ 0x1ff) + 1);
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HALDEBUG(ah, HAL_DEBUG_NFCAL,
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"NF calibrated [ctl] [chain 1] is %d\n", nf);
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nfarray[1] = nf;
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nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
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if (nf & 0x100)
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nf = 0 - ((nf ^ 0x1ff) + 1);
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HALDEBUG(ah, HAL_DEBUG_NFCAL,
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"NF calibrated [ext] [chain 0] is %d\n", nf);
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nfarray[3] = nf;
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nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
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if (nf & 0x100)
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nf = 0 - ((nf ^ 0x1ff) + 1);
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HALDEBUG(ah, HAL_DEBUG_NFCAL,
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"NF calibrated [ext] [chain 1] is %d\n", nf);
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nfarray[4] = nf;
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/* Chain 2 - invalid */
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nfarray[2] = 0;
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nfarray[5] = 0;
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}
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/*
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* Adjust NF based on statistical values for 5GHz frequencies.
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* Stubbed:Not used by Fowl
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*/
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int16_t
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ar9280GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
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{
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return 0;
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}
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/*
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* Free memory for analog bank scratch buffers
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*/
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static void
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ar9280RfDetach(struct ath_hal *ah)
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{
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struct ath_hal_5212 *ahp = AH5212(ah);
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HALASSERT(ahp->ah_rfHal != AH_NULL);
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ath_hal_free(ahp->ah_rfHal);
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ahp->ah_rfHal = AH_NULL;
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}
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HAL_BOOL
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ar9280RfAttach(struct ath_hal *ah, HAL_STATUS *status)
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{
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struct ath_hal_5212 *ahp = AH5212(ah);
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struct ar9280State *priv;
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HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: attach AR9280 radio\n", __func__);
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HALASSERT(ahp->ah_rfHal == AH_NULL);
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priv = ath_hal_malloc(sizeof(struct ar9280State));
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if (priv == AH_NULL) {
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: cannot allocate private state\n", __func__);
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*status = HAL_ENOMEM; /* XXX */
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return AH_FALSE;
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}
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priv->base.rfDetach = ar9280RfDetach;
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priv->base.writeRegs = ar9280WriteRegs;
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priv->base.getRfBank = ar9280GetRfBank;
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priv->base.setChannel = ar9280SetChannel;
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priv->base.setRfRegs = ar9280SetRfRegs;
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priv->base.setPowerTable = ar9280SetPowerTable;
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priv->base.getChannelMaxMinPower = ar9280GetChannelMaxMinPower;
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priv->base.getNfAdjust = ar9280GetNfAdjust;
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ahp->ah_pcdacTable = priv->pcdacTable;
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ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
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ahp->ah_rfHal = &priv->base;
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/*
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* Set noise floor adjust method; we arrange a
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* direct call instead of thunking.
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*/
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AH_PRIVATE(ah)->ah_getNfAdjust = priv->base.getNfAdjust;
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AH_PRIVATE(ah)->ah_getNoiseFloor = ar9280GetNoiseFloor;
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return AH_TRUE;
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}
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static HAL_BOOL
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ar9280RfProbe(struct ath_hal *ah)
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{
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return (AR_SREV_MERLIN(ah));
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}
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AH_RF(RF9280, ar9280RfProbe, ar9280RfAttach);
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