87bdca8290
The atpic_register_sources callback tries to avoid registering interrupt sources that would collide with an I/O APIC. However, the previous implementation was failing to register IRQs 8-15 since the slave PIC saw valid IRQs from the master and assumed an I/O APIC was present. To fix, go back to registering all 8259A interrupt sources in one loop when the master's register_sources method is invoked. PR: 231291 Approved by: re (kib) MFC after: 1 month
634 lines
16 KiB
C
634 lines
16 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* PIC driver for the 8259A Master and Slave PICs in PC/AT machines.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_auto_eoi.h"
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#include "opt_isa.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/interrupt.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <machine/cpufunc.h>
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#include <machine/frame.h>
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#include <machine/intr_machdep.h>
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#include <machine/md_var.h>
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#include <machine/resource.h>
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#include <machine/segments.h>
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#include <dev/ic/i8259.h>
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#include <x86/isa/icu.h>
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#include <isa/isareg.h>
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#include <isa/isavar.h>
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#ifdef __amd64__
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#define SDT_ATPIC SDT_SYSIGT
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#define GSEL_ATPIC 0
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#else
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#define SDT_ATPIC SDT_SYS386IGT
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#define GSEL_ATPIC GSEL(GCODE_SEL, SEL_KPL)
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#endif
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#define MASTER 0
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#define SLAVE 1
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#define IMEN_MASK(ai) (IRQ_MASK((ai)->at_irq))
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#define NUM_ISA_IRQS 16
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static void atpic_init(void *dummy);
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inthand_t
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IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2),
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IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5),
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IDTVEC(atpic_intr6), IDTVEC(atpic_intr7), IDTVEC(atpic_intr8),
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IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11),
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IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14),
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IDTVEC(atpic_intr15);
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/* XXXKIB i386 uses stubs until pti comes */
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inthand_t
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IDTVEC(atpic_intr0_pti), IDTVEC(atpic_intr1_pti),
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IDTVEC(atpic_intr2_pti), IDTVEC(atpic_intr3_pti),
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IDTVEC(atpic_intr4_pti), IDTVEC(atpic_intr5_pti),
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IDTVEC(atpic_intr6_pti), IDTVEC(atpic_intr7_pti),
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IDTVEC(atpic_intr8_pti), IDTVEC(atpic_intr9_pti),
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IDTVEC(atpic_intr10_pti), IDTVEC(atpic_intr11_pti),
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IDTVEC(atpic_intr12_pti), IDTVEC(atpic_intr13_pti),
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IDTVEC(atpic_intr14_pti), IDTVEC(atpic_intr15_pti);
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#define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq)
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#define ATPIC(io, base, eoi) { \
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.at_pic = { \
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.pic_register_sources = atpic_register_sources, \
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.pic_enable_source = atpic_enable_source, \
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.pic_disable_source = atpic_disable_source, \
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.pic_eoi_source = (eoi), \
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.pic_enable_intr = atpic_enable_intr, \
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.pic_disable_intr = atpic_disable_intr, \
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.pic_vector = atpic_vector, \
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.pic_source_pending = atpic_source_pending, \
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.pic_resume = atpic_resume, \
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.pic_config_intr = atpic_config_intr, \
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.pic_assign_cpu = atpic_assign_cpu \
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}, \
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.at_ioaddr = (io), \
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.at_irqbase = (base), \
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.at_intbase = IDT_IO_INTS + (base), \
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.at_imen = 0xff, \
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}
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#define INTSRC(irq) \
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{ { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \
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IDTVEC(atpic_intr ## irq ## _pti), (irq) % 8 }
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struct atpic {
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struct pic at_pic;
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int at_ioaddr;
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int at_irqbase;
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uint8_t at_intbase;
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uint8_t at_imen;
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};
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struct atpic_intsrc {
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struct intsrc at_intsrc;
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inthand_t *at_intr, *at_intr_pti;
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int at_irq; /* Relative to PIC base. */
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enum intr_trigger at_trigger;
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u_long at_count;
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u_long at_straycount;
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};
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static void atpic_register_sources(struct pic *pic);
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static void atpic_enable_source(struct intsrc *isrc);
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static void atpic_disable_source(struct intsrc *isrc, int eoi);
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static void atpic_eoi_master(struct intsrc *isrc);
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static void atpic_eoi_slave(struct intsrc *isrc);
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static void atpic_enable_intr(struct intsrc *isrc);
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static void atpic_disable_intr(struct intsrc *isrc);
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static int atpic_vector(struct intsrc *isrc);
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static void atpic_resume(struct pic *pic, bool suspend_cancelled);
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static int atpic_source_pending(struct intsrc *isrc);
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static int atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
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enum intr_polarity pol);
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static int atpic_assign_cpu(struct intsrc *isrc, u_int apic_id);
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static void i8259_init(struct atpic *pic, int slave);
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static struct atpic atpics[] = {
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ATPIC(IO_ICU1, 0, atpic_eoi_master),
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ATPIC(IO_ICU2, 8, atpic_eoi_slave)
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};
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static struct atpic_intsrc atintrs[] = {
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INTSRC(0),
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INTSRC(1),
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INTSRC(2),
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INTSRC(3),
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INTSRC(4),
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INTSRC(5),
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INTSRC(6),
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INTSRC(7),
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INTSRC(8),
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INTSRC(9),
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INTSRC(10),
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INTSRC(11),
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INTSRC(12),
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INTSRC(13),
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INTSRC(14),
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INTSRC(15),
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};
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CTASSERT(nitems(atintrs) == NUM_ISA_IRQS);
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static __inline void
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_atpic_eoi_master(struct intsrc *isrc)
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{
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KASSERT(isrc->is_pic == &atpics[MASTER].at_pic,
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("%s: mismatched pic", __func__));
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#ifndef AUTO_EOI_1
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outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
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#endif
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}
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/*
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* The data sheet says no auto-EOI on slave, but it sometimes works.
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* So, if AUTO_EOI_2 is enabled, we use it.
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*/
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static __inline void
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_atpic_eoi_slave(struct intsrc *isrc)
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{
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KASSERT(isrc->is_pic == &atpics[SLAVE].at_pic,
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("%s: mismatched pic", __func__));
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#ifndef AUTO_EOI_2
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outb(atpics[SLAVE].at_ioaddr, OCW2_EOI);
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#ifndef AUTO_EOI_1
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outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
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#endif
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#endif
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}
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static void
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atpic_register_sources(struct pic *pic)
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{
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struct atpic *ap = (struct atpic *)pic;
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struct atpic_intsrc *ai;
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int i;
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/*
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* If any of the ISA IRQs have an interrupt source already, then
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* assume that the I/O APICs are being used and don't register any
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* of our interrupt sources. This makes sure we don't accidentally
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* use mixed mode. The "accidental" use could otherwise occur on
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* machines that route the ACPI SCI interrupt to a different ISA
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* IRQ (at least one machine routes it to IRQ 13) thus disabling
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* that APIC ISA routing and allowing the ATPIC source for that IRQ
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* to leak through. We used to depend on this feature for routing
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* IRQ0 via mixed mode, but now we don't use mixed mode at all.
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*
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* To avoid the slave not register sources after the master
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* registers its sources, register all IRQs when this function is
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* called on the master.
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*/
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if (ap != &atpics[MASTER])
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return;
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for (i = 0; i < NUM_ISA_IRQS; i++)
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if (intr_lookup_source(i) != NULL)
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return;
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/* Loop through all interrupt sources and add them. */
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for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
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if (i == ICU_SLAVEID)
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continue;
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intr_register_source(&ai->at_intsrc);
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}
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}
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static void
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atpic_enable_source(struct intsrc *isrc)
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{
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struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
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struct atpic *ap = (struct atpic *)isrc->is_pic;
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spinlock_enter();
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if (ap->at_imen & IMEN_MASK(ai)) {
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ap->at_imen &= ~IMEN_MASK(ai);
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outb(ap->at_ioaddr + ICU_IMR_OFFSET, ap->at_imen);
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}
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spinlock_exit();
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}
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static void
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atpic_disable_source(struct intsrc *isrc, int eoi)
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{
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struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
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struct atpic *ap = (struct atpic *)isrc->is_pic;
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spinlock_enter();
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if (ai->at_trigger != INTR_TRIGGER_EDGE) {
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ap->at_imen |= IMEN_MASK(ai);
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outb(ap->at_ioaddr + ICU_IMR_OFFSET, ap->at_imen);
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}
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/*
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* Take care to call these functions directly instead of through
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* a function pointer. All of the referenced variables should
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* still be hot in the cache.
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*/
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if (eoi == PIC_EOI) {
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if (isrc->is_pic == &atpics[MASTER].at_pic)
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_atpic_eoi_master(isrc);
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else
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_atpic_eoi_slave(isrc);
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}
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spinlock_exit();
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}
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static void
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atpic_eoi_master(struct intsrc *isrc)
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{
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#ifndef AUTO_EOI_1
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spinlock_enter();
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_atpic_eoi_master(isrc);
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spinlock_exit();
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#endif
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}
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static void
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atpic_eoi_slave(struct intsrc *isrc)
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{
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#ifndef AUTO_EOI_2
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spinlock_enter();
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_atpic_eoi_slave(isrc);
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spinlock_exit();
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#endif
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}
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static void
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atpic_enable_intr(struct intsrc *isrc)
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{
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}
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static void
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atpic_disable_intr(struct intsrc *isrc)
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{
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}
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static int
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atpic_vector(struct intsrc *isrc)
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{
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struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
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struct atpic *ap = (struct atpic *)isrc->is_pic;
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return (IRQ(ap, ai));
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}
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static int
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atpic_source_pending(struct intsrc *isrc)
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{
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struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
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struct atpic *ap = (struct atpic *)isrc->is_pic;
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return (inb(ap->at_ioaddr) & IMEN_MASK(ai));
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}
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static void
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atpic_resume(struct pic *pic, bool suspend_cancelled)
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{
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struct atpic *ap = (struct atpic *)pic;
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i8259_init(ap, ap == &atpics[SLAVE]);
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if (ap == &atpics[SLAVE] && elcr_found)
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elcr_resume();
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}
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static int
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atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
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enum intr_polarity pol)
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{
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struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
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u_int vector;
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/* Map conforming values to edge/hi and sanity check the values. */
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if (trig == INTR_TRIGGER_CONFORM)
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trig = INTR_TRIGGER_EDGE;
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if (pol == INTR_POLARITY_CONFORM)
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pol = INTR_POLARITY_HIGH;
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vector = atpic_vector(isrc);
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if ((trig == INTR_TRIGGER_EDGE && pol == INTR_POLARITY_LOW) ||
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(trig == INTR_TRIGGER_LEVEL && pol == INTR_POLARITY_HIGH)) {
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printf(
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"atpic: Mismatched config for IRQ%u: trigger %s, polarity %s\n",
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vector, trig == INTR_TRIGGER_EDGE ? "edge" : "level",
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pol == INTR_POLARITY_HIGH ? "high" : "low");
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return (EINVAL);
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}
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/* If there is no change, just return. */
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if (ai->at_trigger == trig)
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return (0);
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/*
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* Certain IRQs can never be level/lo, so don't try to set them
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* that way if asked. At least some ELCR registers ignore setting
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* these bits as well.
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*/
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if ((vector == 0 || vector == 1 || vector == 2 || vector == 13) &&
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trig == INTR_TRIGGER_LEVEL) {
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if (bootverbose)
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printf(
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"atpic: Ignoring invalid level/low configuration for IRQ%u\n",
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vector);
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return (EINVAL);
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}
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if (!elcr_found) {
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if (bootverbose)
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printf("atpic: No ELCR to configure IRQ%u as %s\n",
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vector, trig == INTR_TRIGGER_EDGE ? "edge/high" :
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"level/low");
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return (ENXIO);
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}
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if (bootverbose)
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printf("atpic: Programming IRQ%u as %s\n", vector,
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trig == INTR_TRIGGER_EDGE ? "edge/high" : "level/low");
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spinlock_enter();
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elcr_write_trigger(atpic_vector(isrc), trig);
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ai->at_trigger = trig;
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spinlock_exit();
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return (0);
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}
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static int
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atpic_assign_cpu(struct intsrc *isrc, u_int apic_id)
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{
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/*
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* 8259A's are only used in UP in which case all interrupts always
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* go to the sole CPU and this function shouldn't even be called.
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*/
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panic("%s: bad cookie", __func__);
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}
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static void
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i8259_init(struct atpic *pic, int slave)
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{
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int imr_addr;
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/* Reset the PIC and program with next four bytes. */
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spinlock_enter();
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outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4);
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imr_addr = pic->at_ioaddr + ICU_IMR_OFFSET;
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/* Start vector. */
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outb(imr_addr, pic->at_intbase);
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/*
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* Setup slave links. For the master pic, indicate what line
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* the slave is configured on. For the slave indicate
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* which line on the master we are connected to.
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*/
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if (slave)
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outb(imr_addr, ICU_SLAVEID);
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else
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outb(imr_addr, IRQ_MASK(ICU_SLAVEID));
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/* Set mode. */
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if (slave)
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outb(imr_addr, SLAVE_MODE);
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else
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outb(imr_addr, MASTER_MODE);
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/* Set interrupt enable mask. */
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outb(imr_addr, pic->at_imen);
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/* Reset is finished, default to IRR on read. */
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outb(pic->at_ioaddr, OCW3_SEL | OCW3_RR);
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/* OCW2_L1 sets priority order to 3-7, 0-2 (com2 first). */
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if (!slave)
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outb(pic->at_ioaddr, OCW2_R | OCW2_SL | OCW2_L1);
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spinlock_exit();
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}
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void
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atpic_startup(void)
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{
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struct atpic_intsrc *ai;
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int i;
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/* Start off with all interrupts disabled. */
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i8259_init(&atpics[MASTER], 0);
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i8259_init(&atpics[SLAVE], 1);
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atpic_enable_source((struct intsrc *)&atintrs[ICU_SLAVEID]);
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/* Install low-level interrupt handlers for all of our IRQs. */
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for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
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if (i == ICU_SLAVEID)
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continue;
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ai->at_intsrc.is_count = &ai->at_count;
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ai->at_intsrc.is_straycount = &ai->at_straycount;
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setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase +
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ai->at_irq, pti ? ai->at_intr_pti : ai->at_intr, SDT_ATPIC,
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SEL_KPL, GSEL_ATPIC);
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}
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/*
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* Look for an ELCR. If we find one, update the trigger modes.
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|
* If we don't find one, assume that IRQs 0, 1, 2, and 13 are
|
|
* edge triggered and that everything else is level triggered.
|
|
* We only use the trigger information to reprogram the ELCR if
|
|
* we have one and as an optimization to avoid masking edge
|
|
* triggered interrupts. For the case that we don't have an ELCR,
|
|
* it doesn't hurt to mask an edge triggered interrupt, so we
|
|
* assume level trigger for any interrupt that we aren't sure is
|
|
* edge triggered.
|
|
*/
|
|
if (elcr_found) {
|
|
for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
|
|
ai->at_trigger = elcr_read_trigger(i);
|
|
} else {
|
|
for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
|
|
switch (i) {
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
case 8:
|
|
case 13:
|
|
ai->at_trigger = INTR_TRIGGER_EDGE;
|
|
break;
|
|
default:
|
|
ai->at_trigger = INTR_TRIGGER_LEVEL;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void
|
|
atpic_init(void *dummy __unused)
|
|
{
|
|
|
|
/*
|
|
* Register our PICs, even if we aren't going to use any of their
|
|
* pins so that they are suspended and resumed.
|
|
*/
|
|
if (intr_register_pic(&atpics[0].at_pic) != 0 ||
|
|
intr_register_pic(&atpics[1].at_pic) != 0)
|
|
panic("Unable to register ATPICs");
|
|
|
|
if (num_io_irqs == 0)
|
|
num_io_irqs = NUM_ISA_IRQS;
|
|
}
|
|
SYSINIT(atpic_init, SI_SUB_INTR, SI_ORDER_FOURTH, atpic_init, NULL);
|
|
|
|
void
|
|
atpic_handle_intr(u_int vector, struct trapframe *frame)
|
|
{
|
|
struct intsrc *isrc;
|
|
|
|
KASSERT(vector < NUM_ISA_IRQS, ("unknown int %u\n", vector));
|
|
isrc = &atintrs[vector].at_intsrc;
|
|
|
|
/*
|
|
* If we don't have an event, see if this is a spurious
|
|
* interrupt.
|
|
*/
|
|
if (isrc->is_event == NULL && (vector == 7 || vector == 15)) {
|
|
int port, isr;
|
|
|
|
/*
|
|
* Read the ISR register to see if IRQ 7/15 is really
|
|
* pending. Reset read register back to IRR when done.
|
|
*/
|
|
port = ((struct atpic *)isrc->is_pic)->at_ioaddr;
|
|
spinlock_enter();
|
|
outb(port, OCW3_SEL | OCW3_RR | OCW3_RIS);
|
|
isr = inb(port);
|
|
outb(port, OCW3_SEL | OCW3_RR);
|
|
spinlock_exit();
|
|
if ((isr & IRQ_MASK(7)) == 0)
|
|
return;
|
|
}
|
|
intr_execute_handlers(isrc, frame);
|
|
}
|
|
|
|
#ifdef DEV_ISA
|
|
/*
|
|
* Bus attachment for the ISA PIC.
|
|
*/
|
|
static struct isa_pnp_id atpic_ids[] = {
|
|
{ 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
|
|
{ 0 }
|
|
};
|
|
|
|
static int
|
|
atpic_probe(device_t dev)
|
|
{
|
|
int result;
|
|
|
|
result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
|
|
if (result <= 0)
|
|
device_quiet(dev);
|
|
return (result);
|
|
}
|
|
|
|
/*
|
|
* We might be granted IRQ 2, as this is typically consumed by chaining
|
|
* between the two PIC components. If we're using the APIC, however,
|
|
* this may not be the case, and as such we should free the resource.
|
|
* (XXX untested)
|
|
*
|
|
* The generic ISA attachment code will handle allocating any other resources
|
|
* that we don't explicitly claim here.
|
|
*/
|
|
static int
|
|
atpic_attach(device_t dev)
|
|
{
|
|
struct resource *res;
|
|
int rid;
|
|
|
|
/* Try to allocate our IRQ and then free it. */
|
|
rid = 0;
|
|
res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 0);
|
|
if (res != NULL)
|
|
bus_release_resource(dev, SYS_RES_IRQ, rid, res);
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Return a bitmap of the current interrupt requests. This is 8259-specific
|
|
* and is only suitable for use at probe time.
|
|
*/
|
|
intrmask_t
|
|
isa_irq_pending(void)
|
|
{
|
|
u_char irr1;
|
|
u_char irr2;
|
|
|
|
irr1 = inb(IO_ICU1);
|
|
irr2 = inb(IO_ICU2);
|
|
return ((irr2 << 8) | irr1);
|
|
}
|
|
|
|
static device_method_t atpic_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, atpic_probe),
|
|
DEVMETHOD(device_attach, atpic_attach),
|
|
DEVMETHOD(device_detach, bus_generic_detach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t atpic_driver = {
|
|
"atpic",
|
|
atpic_methods,
|
|
1, /* no softc */
|
|
};
|
|
|
|
static devclass_t atpic_devclass;
|
|
|
|
DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
|
|
DRIVER_MODULE(atpic, acpi, atpic_driver, atpic_devclass, 0, 0);
|
|
ISA_PNP_INFO(atpic_ids);
|
|
#endif /* DEV_ISA */
|