48115288df
with latch based PPS implementations. The client that uses it will be committed after more testing.
609 lines
15 KiB
C
609 lines
15 KiB
C
/*
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* ----------------------------------------------------------------------------
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* "THE BEER-WARE LICENSE" (Revision 42):
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* <phk@FreeBSD.org> wrote this file. As long as you retain this notice you
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* can do whatever you want with this stuff. If we meet some day, and you think
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* this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
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* ----------------------------------------------------------------------------
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*
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* $Id: loran.c,v 1.5 1998/05/29 08:04:44 phk Exp $
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*
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* This device-driver helps the userland controlprogram for a LORAN-C
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* receiver avoid monopolizing the CPU.
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*
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* This is clearly a candidate for the "most weird hardware support in
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* FreeBSD" prize. At this time only two copies of the receiver are
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* known to exist in the entire world.
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*
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* Details can be found at:
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* ftp://ftp.eecis.udel.edu/pub/ntp/loran.tar.Z
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*
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*/
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#ifdef KERNEL
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#include "loran.h"
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#include "opt_devfs.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/sysctl.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/uio.h>
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#include <sys/syslog.h>
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#include <sys/time.h>
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#include <sys/malloc.h>
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#ifdef DEVFS
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#include <sys/devfsext.h>
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#endif /*DEVFS*/
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#include <i386/isa/isa_device.h>
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#endif /* KERNEL */
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struct datapoint {
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void *ident;
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int index;
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u_int64_t scheduled;
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u_int delay;
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u_int code;
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u_int gri;
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u_int agc;
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u_int phase;
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u_int width;
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u_int par;
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u_int isig;
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u_int qsig;
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u_int ssig;
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u_int64_t epoch;
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struct timespec actual;
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TAILQ_ENTRY(datapoint) list;
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double ival;
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double qval;
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double sval;
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double mval;
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u_char status;
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u_int vco;
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int count;
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int remain;
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};
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/*
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* Mode register (PAR) hardware definitions
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*/
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#define INTEG 0x03 /* integrator mask */
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#define INTEG_1000us 0
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#define INTEG_264us 1
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#define INTEG_36us 2
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#define INTEG_SHORT 3
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#define GATE 0x0C /* gate source mask */
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#define GATE_OPEN 0x0
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#define GATE_GRI 0x4
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#define GATE_PCI 0x8
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#define GATE_STB 0xc
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#define MSB 0x10 /* load dac high-order bits */
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#define IEN 0x20 /* enable interrupt bit */
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#define EN5 0x40 /* enable counter 5 bit */
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#define ENG 0x80 /* enable gri bit */
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#define VCO 2048 /* initial vco dac (0 V)*/
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#ifdef KERNEL
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#define PORT 0x0300 /* controller port address */
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#define PGUARD 990 /* program guard time (cycle) (990!) */
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#define GRI 800 /* pulse-group gate (cycle) */
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/*
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* Analog/digital converter (ADC) hardware definitions
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*/
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#define ADC PORT+2 /* adc buffer (r)/address (w) */
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#define ADCGO PORT+3 /* adc status (r)/adc start (w) */
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#define ADC_START 0x01 /* converter start bit (w) */
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#define ADC_BUSY 0x01 /* converter busy bit (r) */
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#define ADC_DONE 0x80 /* converter done bit (r) */
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#define ADC_I 0 /* i channel (phase) */
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#define ADC_Q 1 /* q channel (amplitude) */
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#define ADC_S 2 /* s channel (agc) */
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/*
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* Digital/analog converter (DAC) hardware definitions
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* Note: output voltage increases with value programmed; the buffer
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* is loaded in two 8-bit bytes, the lsb 8 bits with the MSB bit off in
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* the PAR register, the msb 4 bits with the MSB on.
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*/
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#define DACA PORT+4 /* vco (dac a) buffer (w) */
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#define DACB PORT+5 /* agc (dac b) buffer (w) */
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#define LOAD_DAC(dac, val) if (0) { } else { \
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par &= ~MSB; outb(PAR, par); outb((dac), (val) & 0xff); \
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par |= MSB; outb(PAR, par); outb((dac), ((val) >> 8) & 0xff); \
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}
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/*
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* Pulse-code generator (CODE) hardware definitions
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* Note: bits are shifted out from the lsb first
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*/
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#define CODE PORT+6 /* pulse-code buffer (w) */
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#define MPCA 0xCA /* LORAN-C master pulse code group a */
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#define MPCB 0x9F /* LORAN-C master pulse code group b */
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#define SPCA 0xF9 /* LORAN-C slave pulse code group a */
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#define SPCB 0xAC /* LORAN-C slave pulse code group b */
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/*
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* Mode register (PAR) hardware definitions
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*/
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#define PAR PORT+7 /* parameter buffer (w) */
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#define TGC PORT+0 /* stc control port (r/w) */
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#define TGD PORT+1 /* stc data port (r/w) */
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/*
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* Timing generator (STC) hardware commands
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*/
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/* argument sssss = counter numbers 5-1 */
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#define TG_LOADDP 0x00 /* load data pointer */
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/* argument ee = element (all groups except ggg = 000 or 111) */
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#define MODEREG 0x00 /* mode register */
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#define LOADREG 0x08 /* load register */
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#define HOLDREG 0x10 /* hold register */
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#define HOLDINC 0x18 /* hold register (hold cycle increm) */
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/* argument ee = element (group ggg = 111) */
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#define ALARM1 0x07 /* alarm register 1 */
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#define ALARM2 0x0F /* alarm register 2 */
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#define MASTER 0x17 /* master mode register */
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#define STATUS 0x1F /* status register */
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#define ARM 0x20 /* arm counters */
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#define LOAD 0x40 /* load counters */
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#define TG_LOADARM 0x60 /* load and arm counters */
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#define DISSAVE 0x80 /* disarm and save counters */
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#define TG_SAVE 0xA0 /* save counters */
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#define DISARM 0xC0 /* disarm counters */
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/* argument nnn = counter number */
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#define SETTOG 0xE8 /* set toggle output HIGH for counter */
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#define CLRTOG 0xE0 /* set toggle output LOW for counter */
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#define STEP 0xF0 /* step counter */
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/* argument eeggg, where ee = element, ggg - counter group */
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/* no arguments */
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#define ENABDPS 0xE0 /* enable data pointer sequencing */
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#define ENABFOUT 0xE6 /* enable fout */
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#define ENAB8 0xE7 /* enable 8-bit data bus */
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#define DSABDPS 0xE8 /* disable data pointer sequencing */
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#define ENAB16 0xEF /* enable 16-bit data bus */
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#define DSABFOUT 0xEE /* disable fout */
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#define ENABPFW 0xF8 /* enable prefetch for write */
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#define DSABPFW 0xF9 /* disable prefetch for write */
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#define TG_RESET 0xFF /* master reset */
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#define LOAD_9513(index, val) if (0) {} else { \
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outb(TGC, TG_LOADDP + (index)); \
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outb(TGD, (val) & 0xff); \
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outb(TGD, ((val) >> 8) & 0xff); \
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}
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#define NENV 40 /* size of envelope filter */
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#define CLOCK 50 /* clock period (clock) */
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#define CYCLE 10 /* carrier period (us) */
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#define PCX (NENV * CLOCK) /* envelope gate (clock) */
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#define STROBE 50 /* strobe gate (clock) */
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/**********************************************************************/
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static TAILQ_HEAD(qhead, datapoint) qdone, qready;
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static struct datapoint dummy;
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static u_int64_t ticker;
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static u_char par;
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static struct datapoint *this, *next;
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static MALLOC_DEFINE(M_LORAN, "Loran", "Loran datapoints");
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static int loranerror;
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static char lorantext[80];
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static u_int vco_is;
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static u_int vco_should;
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static int lorantc_magic;
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/**********************************************************************/
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static int loranprobe (struct isa_device *dvp);
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static int loranattach (struct isa_device *isdp);
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static void loranenqueue (struct datapoint *);
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static d_open_t loranopen;
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static d_close_t loranclose;
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static d_read_t loranread;
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static d_write_t loranwrite;
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extern struct timecounter loran_timecounter[];
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/**********************************************************************/
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int
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loranprobe(struct isa_device *dvp)
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{
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/* We need to be a "fast-intr" */
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dvp->id_ri_flags |= RI_FAST;
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dvp->id_iobase = PORT;
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return (8);
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}
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u_short tg_init[] = { /* stc initialization vector */
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0x0562, 12, 13, /* counter 1 (p0) */
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0x0262, PGUARD, GRI, /* counter 2 (gri) */
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0x8562, PCX, 5000 - PCX, /* counter 3 (pcx) */
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0xc562, 0, STROBE, /* counter 4 (stb) */
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0x052a, 0, 0 /* counter 5 (out) */
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};
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void
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init_tgc(void)
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{
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int i;
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/* Initialize the 9513A */
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outb(TGC, TG_RESET); outb(TGC, LOAD+0x1f); /* reset STC chip */
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LOAD_9513(MASTER, 0x8af0);
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outb(TGC, TG_LOADDP+1);
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tg_init[4] = 7499 - GRI;
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for (i = 0; i < 5*3; i++) {
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outb(TGD, tg_init[i]);
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outb(TGD, tg_init[i] >> 8);
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}
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outb(TGC, TG_LOADARM+0x1f); /* let the good times roll */
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}
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int
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loranattach(struct isa_device *isdp)
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{
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int i;
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/* We need to be a "fast-intr" */
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isdp->id_ri_flags |= RI_FAST;
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printf("loran0: LORAN-C Receiver\n");
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vco_is = VCO;
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LOAD_DAC(DACA, VCO);
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init_tgc();
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init_timecounter(loran_timecounter);
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TAILQ_INIT(&qdone);
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TAILQ_INIT(&qready);
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dummy.agc = 4095;
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dummy.code = 0xac;
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dummy.delay = PGUARD - GRI;
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dummy.gri = PGUARD;
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dummy.phase = 50;
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dummy.width = 50;
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TAILQ_INSERT_HEAD(&qready, &dummy, list);
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this = &dummy;
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next = &dummy;
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inb(ADC); /* Flush any old result */
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outb(ADC, ADC_S);
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par = ENG|IEN;
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outb(PAR, par);
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return (1);
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}
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static int
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loranopen (dev_t dev, int flags, int fmt, struct proc *p)
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{
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u_long ef;
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struct datapoint *this;
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while (!TAILQ_EMPTY(&qdone)) {
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ef = read_eflags();
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disable_intr();
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this = TAILQ_FIRST(&qdone);
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TAILQ_REMOVE(&qdone, this, list);
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write_eflags(ef);
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FREE(this, M_LORAN);
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}
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init_tgc();
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loranerror = 0;
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return(0);
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}
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static int
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loranclose(dev_t dev, int flags, int fmt, struct proc *p)
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{
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/*
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* Lower ENG
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*/
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return(0);
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}
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static int
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loranread(dev_t dev, struct uio * uio, int ioflag)
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{
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u_long ef;
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struct datapoint *this;
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int err, c;
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if (loranerror) {
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printf("Loran0: %s", lorantext);
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return(EIO);
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}
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if (TAILQ_EMPTY(&qdone))
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tsleep ((caddr_t)&qdone, PZERO + 8 |PCATCH, "loranrd", hz*2);
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if (TAILQ_EMPTY(&qdone))
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return(0);
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this = TAILQ_FIRST(&qdone);
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ef = read_eflags();
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disable_intr();
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TAILQ_REMOVE(&qdone, this, list);
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write_eflags(ef);
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c = imin(uio->uio_resid, (int)sizeof *this);
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err = uiomove((caddr_t)this, c, uio);
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FREE(this, M_LORAN);
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return(err);
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}
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static void
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loranenqueue(struct datapoint *this)
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{
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struct datapoint *p, *q;
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u_long ef;
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u_int64_t x;
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if (this->scheduled < ticker) {
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x = (ticker - this->scheduled) / (2 * this->gri);
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this->scheduled += x * 2 * this->gri;
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}
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ef = read_eflags();
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disable_intr();
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p = TAILQ_FIRST(&qready);
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while (1) {
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while (this->scheduled < p->scheduled + PGUARD)
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this->scheduled += 2 * this->gri;
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q = TAILQ_NEXT(p, list);
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if (!q) {
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this->delay = this->scheduled - p->scheduled - GRI;
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TAILQ_INSERT_TAIL(&qready, this, list);
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break;
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}
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if (this->scheduled + PGUARD < q->scheduled) {
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this->delay = this->scheduled - p->scheduled - GRI;
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TAILQ_INSERT_BEFORE(q, this, list);
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q->delay = q->scheduled - this->scheduled - GRI;
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break;
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}
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p = q;
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}
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write_eflags(ef);
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}
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static int
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loranwrite(dev_t dev, struct uio * uio, int ioflag)
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{
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int err = 0, c;
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struct datapoint *this;
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MALLOC(this, struct datapoint *, sizeof *this, M_LORAN, M_WAITOK);
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c = imin(uio->uio_resid, (int)sizeof *this);
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err = uiomove((caddr_t)this, c, uio);
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if (!err && this->gri == 0)
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err = EINVAL;
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if (!err) {
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loranenqueue(this);
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vco_should = this->vco;
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} else {
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FREE(this, M_LORAN);
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}
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return(err);
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}
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void
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loranintr(int unit)
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{
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u_long ef;
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int status = 0, count = 0, i;
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ef = read_eflags();
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disable_intr();
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if (this != &dummy) {
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outb(TGC, DSABDPS);
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outb(TGC, TG_LOADDP + 0x12); /* hold counter #2 */
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this->remain = -1;
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i = 2;
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for (i = 0; i < 2; i++) {
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count = this->remain;
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do {
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outb(TGC, TG_SAVE + 0x12);
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this->remain = inb(TGD) & 0xff;
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this->remain |= inb(TGD) << 8;
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} while (count == this->remain);
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}
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lorantc_magic = 1;
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nanotime(&this->actual);
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lorantc_magic = 0;
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outb(TGC, TG_LOADDP + 0x0a);
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this->count = inb(TGD);
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this->count |= inb(TGD) << 8;
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LOAD_9513(0x12, GRI)
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}
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this->ssig = inb(ADC);
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par &= ~(ENG | IEN);
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outb(PAR, par);
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outb(ADC, ADC_I);
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outb(ADCGO, ADC_START);
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while (!(inb(ADCGO) & ADC_DONE))
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continue;
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this->isig = inb(ADC);
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outb(ADC, ADC_Q);
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outb(ADCGO, ADC_START);
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while (!(inb(ADCGO) & ADC_DONE))
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continue;
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this->qsig = inb(ADC);
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outb(ADC, ADC_S);
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this->epoch = ticker;
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if (this != &dummy) {
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TAILQ_INSERT_TAIL(&qdone, this, list);
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wakeup((caddr_t)&qdone);
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}
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if (next != &dummy || TAILQ_NEXT(next, list))
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TAILQ_REMOVE(&qready, next, list);
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this = next;
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ticker += GRI;
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ticker += this->delay;
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next = TAILQ_FIRST(&qready);
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if (!next) {
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next = &dummy;
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TAILQ_INSERT_HEAD(&qready, next, list);
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} else if (next->delay + GRI > PGUARD * 2) {
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next->delay -= PGUARD;
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next = &dummy;
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TAILQ_INSERT_HEAD(&qready, next, list);
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}
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if (next == &dummy)
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next->scheduled = ticker + GRI + next->delay;
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/* load this->params */
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par &= ~(INTEG|GATE);
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par |= this->par & (INTEG|GATE);
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LOAD_DAC(DACB, this->agc);
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outb(CODE, this->code);
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LOAD_9513(0x0a, next->delay);
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/*
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* We need to load this from the opposite register * due to some
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* weirdness which you can read about in in the 9513 manual on
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* page 1-26 under "LOAD"
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*/
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LOAD_9513(0x0c, this->phase);
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LOAD_9513(0x14, this->phase);
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outb(TGC, TG_LOADARM + 0x08);
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LOAD_9513(0x14, this->width);
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if (vco_is != vco_should) {
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LOAD_DAC(DACA, vco_should);
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vco_is = vco_should;
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}
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this->status = inb(TGC);
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|
#if 1
|
|
/* Check if we overran */
|
|
status = this->status & 0x1c;
|
|
|
|
if (status) {
|
|
outb(TGC, TG_SAVE + 2); /* save counter #2 */
|
|
outb(TGC, TG_LOADDP + 0x12); /* hold counter #2 */
|
|
count = inb(TGD);
|
|
count |= inb(TGD) << 8;
|
|
LOAD_9513(0x12, GRI)
|
|
}
|
|
#endif
|
|
|
|
par |= ENG | IEN;
|
|
outb(PAR, par);
|
|
|
|
if (status) {
|
|
sprintf(lorantext, "Missed: %02x %d %d this:%p next:%p (dummy=%p)\n",
|
|
status, count, next->delay, this, next, &dummy);
|
|
loranerror = 1;
|
|
}
|
|
if (next->delay < PGUARD - GRI) {
|
|
sprintf(lorantext, "Bogus: %02x %d %d\n",
|
|
status, count, next->delay);
|
|
loranerror = 1;
|
|
}
|
|
|
|
write_eflags(ef);
|
|
}
|
|
|
|
/**********************************************************************/
|
|
|
|
static unsigned
|
|
loran_get_timecount(void)
|
|
{
|
|
unsigned count;
|
|
u_long ef;
|
|
u_int high, low;
|
|
|
|
ef = read_eflags();
|
|
disable_intr();
|
|
|
|
if (!lorantc_magic)
|
|
outb(TGC, TG_SAVE + 0x10); /* save counter #5 */
|
|
outb(TGC, TG_LOADDP +0x15); /* hold counter #5 */
|
|
count = inb(TGD);
|
|
count |= inb(TGD) << 8;
|
|
|
|
write_eflags(ef);
|
|
return (count);
|
|
}
|
|
|
|
static struct timecounter loran_timecounter[3] = {
|
|
loran_get_timecount, /* get_timecount */
|
|
0, /* no pps_poll */
|
|
0xffff, /* counter_mask */
|
|
5000000, /* frequency */
|
|
"loran" /* name */
|
|
};
|
|
|
|
SYSCTL_OPAQUE(_debug, OID_AUTO, loran_timecounter, CTLFLAG_RD,
|
|
loran_timecounter, sizeof(loran_timecounter), "S,timecounter", "");
|
|
|
|
|
|
/**********************************************************************/
|
|
|
|
struct isa_driver lorandriver = {
|
|
loranprobe, loranattach, "loran"
|
|
};
|
|
|
|
#define CDEV_MAJOR 94
|
|
static struct cdevsw loran_cdevsw =
|
|
{ loranopen, loranclose, loranread, loranwrite,
|
|
noioctl, nullstop, nullreset, nodevtotty,
|
|
seltrue, nommap, nostrat, "loran",
|
|
NULL, -1 };
|
|
|
|
|
|
static loran_devsw_installed = 0;
|
|
|
|
static void loran_drvinit(void *unused)
|
|
{
|
|
dev_t dev;
|
|
|
|
if(!loran_devsw_installed) {
|
|
dev = makedev(CDEV_MAJOR, 0);
|
|
cdevsw_add(&dev,&loran_cdevsw, NULL);
|
|
loran_devsw_installed = 1;
|
|
}
|
|
}
|
|
|
|
SYSINIT(lorandev,SI_SUB_DRIVERS,SI_ORDER_MIDDLE+CDEV_MAJOR,loran_drvinit,NULL)
|
|
|
|
#endif /* KERNEL */
|