8912c0ed61
/usr/src/sys/i386/isa/clock.c: o Garrett's statclock changes. o Wire xxxintr, not Vclk. o Wire using register_intr(), not setidt(). /usr/src/sys/i386/isa/icu.s: o Garrett's statclock changes. o Removed unused variable high_imask. o Fake int 8 for rtc as well as int 0 for clk. Required for kernel profiling with statclock, harmless otherwise. /usr/src/sys/i386/isa/isa.c: o Allow isdp->id_irq and other things in *isdp to be changed by probes. Changing interrupts later requires direct calls to register_intr() and unregister_intr() and more care. ALLOW_CONFLICT_* is brought over from 1.1.5, except ALLOW_CONFLICT_IRQ is not supported. IRQ conflict checking is delayed until after probing so that drivers can change the IRQ to a free one; real conflicts require more cooperation between drivers to handle. o Too many details to list. o This file requires splitting and a lot more work. /usr/src/sys/i386/isa/isa_device.h: o Declare more things more completely. /usr/src/sys/i386/isa/sio.c: o Prepare to register interrupt handlers as fast. /usr/src/sys/i386/isa/vector.s: o Generate entry code for 16 fast interrupt handlers and 16 normal interrupt handlers. Changed some constants to variables: # $unit is now intr_unit[intr]. Type is int. Someday it should be a cookie suitable for the handler (e.g., a struct com_s for sio). # $handler is now intr_handler[intr]. # intrcnt_actv[id_num] is now *intr_countp[intr]. The indirection is required to get a contiguous range of counters for vmstat and so that the drivers depend more in the driver than on the interrupt number (drivers could take turns using an interrupt and the counts would remain correct). There is a separate counter for each device and for each stray interrupt. In 1.1.5, stray interrupt 7 clobbers the count for device 7 or something worse if there is no device 7 :-(. # mask is now intr_mask[intr] (was already indirect). o Entry points are now _XintrI and _XfastintrI (I = intr = 0-15), not _VdevU (U = unit). o Removed BUILD_VECTORS stuff. There's a trace of it left for the string table for vmstat but config now generates the string in one piece because nothing more is required. o Removed old handling of stray interrupts and older comments about it. Submitted by: Bruce Evans
542 lines
13 KiB
C
542 lines
13 KiB
C
/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz and Don Ahn.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.14 1994/08/15 03:15:18 wollman Exp $
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*/
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/*
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* Primitive clock interrupt routines.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/time.h>
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#include <sys/kernel.h>
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#include <machine/segments.h>
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#include <machine/frame.h>
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#include <i386/isa/icu.h>
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#include <i386/isa/isa.h>
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#include <i386/isa/rtc.h>
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#include <i386/isa/timerreg.h>
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#include <machine/cpu.h>
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/* X-tals being what they are, it's nice to be able to fudge this one... */
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/* Note, the name changed here from XTALSPEED to TIMER_FREQ rgrimes 4/26/93 */
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#ifndef TIMER_FREQ
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#define TIMER_FREQ 1193182 /* XXX - should be in isa.h */
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#endif
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#define TIMER_DIV(x) ((TIMER_FREQ+(x)/2)/(x))
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void hardclock();
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void statclock();
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static int beeping;
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int timer0_divisor = TIMER_DIV(100); /* XXX should be hz */
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u_int timer0_prescale;
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static char timer0_state = 0, timer2_state = 0;
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static char timer0_reprogram = 0;
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static void (*timer_func)() = hardclock;
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static void (*new_function)();
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static u_int new_rate;
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static u_int hardclock_divisor;
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#ifdef I586_CPU
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int pentium_mhz = 0;
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#endif
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void
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clkintr(frame)
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struct clockframe frame;
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{
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#ifdef I586_CPU
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/*
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* This resets the CPU cycle counter to zero, to make our
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* job easier in microtime(). Some fancy ifdefs could speed
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* this up for Pentium-only kernels.
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* We want this to be done as close as possible to the actual
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* timer incrementing in hardclock(), because there is a window
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* between the two where the value is no longer valid. Experimentation
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* may reveal a good precompensation to apply in microtime().
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*/
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if(pentium_mhz) {
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__asm __volatile("movl $0x10,%%ecx\n"
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"xorl %%eax,%%eax\n"
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"movl %%eax,%%edx\n"
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".byte 0x0f, 0x30\n"
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"#%0%1"
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: "=m"(frame) /* no outputs */
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: "b"(&frame) /* fake input */
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: "ax", "cx", "dx");
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}
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#endif
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hardclock(&frame);
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}
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static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
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/*
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* This routine receives statistical clock interrupts from the RTC.
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* As explained above, these occur at 128 interrupts per second.
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* When profiling, we receive interrupts at a rate of 1024 Hz.
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*
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* This does not actually add as much overhead as it sounds, because
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* when the statistical clock is active, the hardclock driver no longer
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* needs to keep (inaccurate) statistics on its own. This decouples
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* statistics gathering from scheduling interrupts.
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*
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* The RTC chip requires that we read status register C (RTC_INTR)
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* to acknowledge an interrupt, before it will generate the next one.
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*/
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void
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rtcintr(struct clockframe frame)
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{
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u_char stat;
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stat = rtcin(RTC_INTR);
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if(stat & RTCIR_PERIOD) {
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statclock(&frame);
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}
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}
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#ifdef DEBUG
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void
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printrtc(void)
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{
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outb(IO_RTC, RTC_STATUSA);
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printf("RTC status A = %x", inb(IO_RTC+1));
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outb(IO_RTC, RTC_STATUSB);
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printf(", B = %x", inb(IO_RTC+1));
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outb(IO_RTC, RTC_INTR);
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printf(", C = %x\n", inb(IO_RTC+1));
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}
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#endif
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#if 0
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void
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timerintr(struct clockframe frame)
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{
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timer_func(&frame);
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switch (timer0_state) {
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case 0:
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break;
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case 1:
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if ((timer0_prescale+=timer0_divisor) >= hardclock_divisor) {
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hardclock(&frame);
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timer0_prescale = 0;
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}
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break;
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case 2:
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disable_intr();
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outb(TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT);
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outb(TIMER_CNTR0, TIMER_DIV(new_rate)%256);
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outb(TIMER_CNTR0, TIMER_DIV(new_rate)/256);
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enable_intr();
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timer0_divisor = TIMER_DIV(new_rate);
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timer0_prescale = 0;
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timer_func = new_function;
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timer0_state = 1;
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break;
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case 3:
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if ((timer0_prescale+=timer0_divisor) >= hardclock_divisor) {
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hardclock(&frame);
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disable_intr();
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outb(TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT);
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outb(TIMER_CNTR0, TIMER_DIV(hz)%256);
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outb(TIMER_CNTR0, TIMER_DIV(hz)/256);
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enable_intr();
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timer0_divisor = TIMER_DIV(hz);
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timer0_prescale = 0;
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timer_func = hardclock;;
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timer0_state = 0;
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}
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break;
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}
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}
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#endif
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int
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acquire_timer0(int rate, void (*function)() )
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{
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if (timer0_state || !function)
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return -1;
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new_function = function;
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new_rate = rate;
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timer0_state = 2;
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return 0;
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}
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int
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acquire_timer2(int mode)
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{
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if (timer2_state)
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return -1;
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timer2_state = 1;
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outb(TIMER_MODE, TIMER_SEL2 | (mode &0x3f));
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return 0;
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}
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int
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release_timer0()
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{
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if (!timer0_state)
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return -1;
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timer0_state = 3;
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return 0;
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}
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int
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release_timer2()
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{
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if (!timer2_state)
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return -1;
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timer2_state = 0;
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outb(TIMER_MODE, TIMER_SEL2|TIMER_SQWAVE|TIMER_16BIT);
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return 0;
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}
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static int
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getit()
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{
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int high, low;
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disable_intr();
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/* select timer0 and latch counter value */
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outb(TIMER_MODE, TIMER_SEL0);
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low = inb(TIMER_CNTR0);
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high = inb(TIMER_CNTR0);
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enable_intr();
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return ((high << 8) | low);
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}
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#ifdef I586_CPU
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static long long cycles_per_sec = 0;
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/*
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* Figure out how fast the cyclecounter runs. This must be run with
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* clock interrupts disabled, but with the timer/counter programmed
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* and running.
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*/
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void
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calibrate_cyclecounter(void)
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{
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volatile long edx, eax, lasteax, lastedx;
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__asm __volatile(".byte 0x0f, 0x31" : "=a"(lasteax), "=d"(lastedx) : );
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DELAY(1000000);
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__asm __volatile(".byte 0x0f, 0x31" : "=a"(eax), "=d"(edx) : );
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/*
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* This assumes that you will never have a clock rate higher
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* than 4GHz, probably a good assumption.
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*/
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cycles_per_sec = (long long)edx + eax;
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cycles_per_sec -= (long long)lastedx + lasteax;
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pentium_mhz = ((long)cycles_per_sec + 500000) / 1000000; /* round up */
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}
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#endif
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/*
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* Wait "n" microseconds.
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* Relies on timer 1 counting down from (TIMER_FREQ / hz)
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* Note: timer had better have been programmed before this is first used!
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*/
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void
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DELAY(int n)
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{
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int counter_limit, prev_tick, tick, ticks_left, sec, usec;
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#ifdef DELAYDEBUG
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int getit_calls = 1;
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int n1;
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static int state = 0;
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if (state == 0) {
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state = 1;
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for (n1 = 1; n1 <= 10000000; n1 *= 10)
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DELAY(n1);
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state = 2;
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}
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if (state == 1)
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printf("DELAY(%d)...", n);
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#endif
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/*
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* Read the counter first, so that the rest of the setup overhead is
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* counted. Guess the initial overhead is 20 usec (on most systems it
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* takes about 1.5 usec for each of the i/o's in getit(). The loop
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* takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
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* multiplications and divisions to scale the count take a while).
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*/
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prev_tick = getit(0, 0);
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n -= 20;
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/*
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* Calculate (n * (TIMER_FREQ / 1e6)) without using floating point
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* and without any avoidable overflows.
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*/
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sec = n / 1000000;
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usec = n - sec * 1000000;
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ticks_left = sec * TIMER_FREQ
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+ usec * (TIMER_FREQ / 1000000)
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+ usec * ((TIMER_FREQ % 1000000) / 1000) / 1000
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+ usec * (TIMER_FREQ % 1000) / 1000000;
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while (ticks_left > 0) {
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tick = getit(0, 0);
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#ifdef DELAYDEBUG
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++getit_calls;
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#endif
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if (tick > prev_tick)
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ticks_left -= prev_tick - (tick - timer0_divisor);
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else
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ticks_left -= prev_tick - tick;
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prev_tick = tick;
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}
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#ifdef DELAYDEBUG
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if (state == 1)
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printf(" %d calls to getit() at %d usec each\n",
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getit_calls, (n + 5) / getit_calls);
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#endif
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}
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static void
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sysbeepstop()
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{
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outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
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release_timer2();
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beeping = 0;
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}
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int
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sysbeep(int pitch, int period)
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{
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if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
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return -1;
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disable_intr();
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outb(TIMER_CNTR2, pitch);
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outb(TIMER_CNTR2, (pitch>>8));
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enable_intr();
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if (!beeping) {
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outb(IO_PPI, inb(IO_PPI) | 3); /* enable counter2 output to speaker */
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beeping = period;
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timeout(sysbeepstop, 0, period);
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}
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return 0;
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}
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void
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startrtclock()
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{
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int s;
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/* initialize 8253 clock */
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outb(TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT);
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/* Correct rounding will buy us a better precision in timekeeping */
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outb (IO_TIMER1, TIMER_DIV(hz)%256);
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outb (IO_TIMER1, TIMER_DIV(hz)/256);
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timer0_divisor = hardclock_divisor = TIMER_DIV(hz);
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/* initialize brain-dead battery powered clock */
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outb (IO_RTC, RTC_STATUSA);
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outb (IO_RTC+1, rtc_statusa);
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outb (IO_RTC, RTC_STATUSB);
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outb (IO_RTC+1, RTCSB_24HR);
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outb (IO_RTC, RTC_DIAG);
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if (s = inb (IO_RTC+1))
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printf("RTC BIOS diagnostic error %b\n", s, RTCDG_BITS);
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}
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/* convert 2 digit BCD number */
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int
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bcd(int i)
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{
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return ((i/16)*10 + (i%16));
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}
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/* convert years to seconds (from 1970) */
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unsigned long
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ytos(int y)
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{
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int i;
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unsigned long ret;
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ret = 0;
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for(i = 1970; i < y; i++) {
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if (i % 4) ret += 365*24*60*60;
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else ret += 366*24*60*60;
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}
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return ret;
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}
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/* convert months to seconds */
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unsigned long
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mtos(int m, int leap)
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{
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int i;
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unsigned long ret;
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ret = 0;
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for(i=1; i<m; i++) {
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switch(i){
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case 1: case 3: case 5: case 7: case 8: case 10: case 12:
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ret += 31*24*60*60; break;
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case 4: case 6: case 9: case 11:
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ret += 30*24*60*60; break;
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case 2:
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if (leap) ret += 29*24*60*60;
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else ret += 28*24*60*60;
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}
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}
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return ret;
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}
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|
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/*
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* Initialize the time of day register, based on the time base which is, e.g.
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* from a filesystem.
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*/
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void
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inittodr(time_t base)
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{
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unsigned long sec;
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int leap, day_week, t, yd;
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int sa,s;
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/* do we have a realtime clock present? (otherwise we loop below) */
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sa = rtcin(RTC_STATUSA);
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if (sa == 0xff || sa == 0) return;
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/* ready for a read? */
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while ((sa&RTCSA_TUP) == RTCSA_TUP)
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sa = rtcin(RTC_STATUSA);
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sec = bcd(rtcin(RTC_YEAR)) + 1900;
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if (sec < 1970)
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sec += 100;
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leap = !(sec % 4); sec = ytos(sec); /* year */
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yd = mtos(bcd(rtcin(RTC_MONTH)),leap); sec+=yd; /* month */
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t = (bcd(rtcin(RTC_DAY))-1) * 24*60*60; sec+=t; yd+=t; /* date */
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day_week = rtcin(RTC_WDAY); /* day */
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sec += bcd(rtcin(RTC_HRS)) * 60*60; /* hour */
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sec += bcd(rtcin(RTC_MIN)) * 60; /* minutes */
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sec += bcd(rtcin(RTC_SEC)); /* seconds */
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sec += tz.tz_minuteswest * 60;
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time.tv_sec = sec;
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}
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|
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#ifdef garbage
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/*
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* Initialze the time of day register, based on the time base which is, e.g.
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* from a filesystem.
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*/
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test_inittodr(time_t base)
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{
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outb(IO_RTC,9); /* year */
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printf("%d ",bcd(inb(IO_RTC+1)));
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outb(IO_RTC,8); /* month */
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printf("%d ",bcd(inb(IO_RTC+1)));
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outb(IO_RTC,7); /* day */
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printf("%d ",bcd(inb(IO_RTC+1)));
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outb(IO_RTC,4); /* hour */
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printf("%d ",bcd(inb(IO_RTC+1)));
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outb(IO_RTC,2); /* minutes */
|
|
printf("%d ",bcd(inb(IO_RTC+1)));
|
|
outb(IO_RTC,0); /* seconds */
|
|
printf("%d\n",bcd(inb(IO_RTC+1)));
|
|
|
|
time.tv_sec = base;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Wire clock interrupt in.
|
|
*/
|
|
void
|
|
enablertclock()
|
|
{
|
|
register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, clkintr,
|
|
HWI_MASK | SWI_MASK, /* unit */ 0);
|
|
INTREN(IRQ0);
|
|
register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, rtcintr,
|
|
SWI_CLOCK_MASK, /* unit */ 0);
|
|
INTREN(IRQ8);
|
|
outb(IO_RTC, RTC_STATUSB);
|
|
outb(IO_RTC+1, RTCSB_PINTR | RTCSB_24HR);
|
|
}
|
|
|
|
|
|
/*
|
|
* Delay for some number of milliseconds.
|
|
*/
|
|
void
|
|
spinwait(int millisecs)
|
|
{
|
|
DELAY(1000 * millisecs);
|
|
}
|
|
|
|
void
|
|
cpu_initclocks()
|
|
{
|
|
stathz = RTC_NOPROFRATE;
|
|
profhz = RTC_PROFRATE;
|
|
enablertclock();
|
|
}
|
|
|
|
void
|
|
setstatclockrate(int newhz)
|
|
{
|
|
if(newhz == RTC_PROFRATE) {
|
|
rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
|
|
} else {
|
|
rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
|
|
}
|
|
outb(IO_RTC, RTC_STATUSA);
|
|
outb(IO_RTC+1, rtc_statusa);
|
|
}
|