89290aa383
shared code infrastructure that is family specific and modular. There is also support for our latest gigabit nic, the 82575 that is MSI/X and multiqueue capable. The new shared code changes some interfaces to the core code but testing at Intel has been going on for months, it is fairly stable. I have attempted to be careful in retaining any fixes that CURRENT had and we did not, I apologize in advance if any thing gets clobbered, I'm sure I'll hear about it :) Approved by pdeuskar
189 lines
7.2 KiB
C
189 lines
7.2 KiB
C
/**************************************************************************
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Copyright (c) 2001-2007, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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***************************************************************************/
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$FreeBSD$
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#ifndef _FREEBSD_OS_H_
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#define _FREEBSD_OS_H_
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/protosw.h>
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#include <sys/socket.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <machine/resource.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/clock.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#define ASSERT(x) if(!(x)) panic("EM: x")
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/* The happy-fun DELAY macro is defined in /usr/src/sys/i386/include/clock.h */
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#define usec_delay(x) DELAY(x)
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#define msec_delay(x) DELAY(1000*(x))
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/* TODO: Should we be paranoid about delaying in interrupt context? */
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#define msec_delay_irq(x) DELAY(1000*(x))
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#define MSGOUT(S, A, B) printf(S "\n", A, B)
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#define DEBUGFUNC(F) DEBUGOUT(F);
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#define DEBUGOUT(S)
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#define DEBUGOUT1(S,A)
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#define DEBUGOUT2(S,A,B)
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#define DEBUGOUT3(S,A,B,C)
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#define DEBUGOUT7(S,A,B,C,D,E,F,G)
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#define STATIC static
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#define FALSE 0
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#define TRUE 1
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#define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
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#define PCI_COMMAND_REGISTER PCIR_COMMAND
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/*
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** These typedefs are necessary due to the new
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** shared code, they are native to Linux.
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*/
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typedef uint64_t u64;
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typedef uint32_t u32;
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typedef uint16_t u16;
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typedef uint8_t u8;
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typedef int64_t s64;
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typedef int32_t s32;
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typedef int16_t s16;
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typedef int8_t s8;
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struct e1000_osdep
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{
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bus_space_tag_t mem_bus_space_tag;
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bus_space_handle_t mem_bus_space_handle;
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bus_space_tag_t io_bus_space_tag;
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bus_space_handle_t io_bus_space_handle;
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bus_space_tag_t flash_bus_space_tag;
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bus_space_handle_t flash_bus_space_handle;
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struct device *dev;
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};
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#ifdef NO_82542_SUPPORT
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#define E1000_REGISTER(hw, reg) reg
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#else
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#define E1000_REGISTER(hw, reg) (((hw)->mac.type >= e1000_82543) \
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? reg : e1000_translate_register_82542(reg))
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#endif
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#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
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/* Read from an absolute offset in the adapter's memory space */
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#define E1000_READ_OFFSET(hw, offset) \
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bus_space_read_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
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((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, offset)
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/* Write to an absolute offset in the adapter's memory space */
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#define E1000_WRITE_OFFSET(hw, offset, value) \
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bus_space_write_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
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((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, offset, value)
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/* Register READ/WRITE macros */
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#define E1000_READ_REG(hw, reg) \
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bus_space_read_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
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((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
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E1000_REGISTER(hw, reg))
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#define E1000_WRITE_REG(hw, reg, value) \
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bus_space_write_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
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((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
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E1000_REGISTER(hw, reg), value)
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#define E1000_READ_REG_ARRAY(hw, reg, index) \
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bus_space_read_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
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((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
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E1000_REGISTER(hw, reg) + ((index)<< 2))
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#define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \
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bus_space_write_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
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((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
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E1000_REGISTER(hw, reg) + ((index)<< 2), value)
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#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
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#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
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#define E1000_READ_REG_ARRAY_BYTE(hw, reg, index) \
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bus_space_read_1(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
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((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
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E1000_REGISTER(hw, reg) + index)
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#define E1000_WRITE_REG_ARRAY_BYTE(hw, reg, index, value) \
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bus_space_write_1(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
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((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
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E1000_REGISTER(hw, reg) + index, value)
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#define E1000_WRITE_REG_ARRAY_WORD(hw, reg, index, value) \
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bus_space_write_2(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
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((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
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E1000_REGISTER(hw, reg) + (index << 1), value)
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#define E1000_WRITE_REG_IO(hw, reg, value) do {\
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bus_space_write_4(((struct e1000_osdep *)(hw)->back)->io_bus_space_tag, \
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((struct e1000_osdep *)(hw)->back)->io_bus_space_handle, \
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(hw)->io_base, reg); \
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bus_space_write_4(((struct e1000_osdep *)(hw)->back)->io_bus_space_tag, \
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((struct e1000_osdep *)(hw)->back)->io_bus_space_handle, \
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(hw)->io_base + 4, value); } while (0)
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#define E1000_READ_FLASH_REG(hw, reg) \
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bus_space_read_4(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \
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((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg)
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#define E1000_READ_FLASH_REG16(hw, reg) \
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bus_space_read_2(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \
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((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg)
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#define E1000_WRITE_FLASH_REG(hw, reg, value) \
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bus_space_write_4(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \
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((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg, value)
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#define E1000_WRITE_FLASH_REG16(hw, reg, value) \
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bus_space_write_2(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \
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((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg, value)
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#endif /* _FREEBSD_OS_H_ */
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