159 lines
5.3 KiB
C
159 lines
5.3 KiB
C
/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* from: NetBSD: hmevar.h,v 1.5 2000/06/25 01:10:04 eeh Exp
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*
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* $FreeBSD$
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*/
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#include <sys/callout.h>
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/*
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* Number of receive and transmit descriptors. For each receive descriptor,
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* an mbuf cluster is allocated and set up to receive a packet, and a dma map
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* is created. Therefore, this number should not be too high to not waste
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* memory.
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* TX descriptors have no static cost, except for the memory directly allocated
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* for them. TX queue elements (the number of which is fixed by HME_NTXQ) hold
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* the software state for a transmit job; each has a dmamap allocated for it.
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* There may be multiple descriptors allocated to a single queue element.
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* HME_NTXQ and HME_NTXSEGS are completely arbitrary.
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*/
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#define HME_NRXDESC 128
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#define HME_NTXDESC 256
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#define HME_NTXQ 64
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#define HME_NTXSEGS 16
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/* Maximum size of a mapped RX buffer. */
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#define HME_BUFSZ 1600
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/*
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* RX DMA descriptor. The descriptors are preallocated; the dma map is
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* reused.
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*/
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struct hme_rxdesc {
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struct mbuf *hrx_m;
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bus_dmamap_t hrx_dmamap;
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};
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/* Lazily leave at least one burst size grace space. */
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#define HME_DESC_RXLEN(sc, d) \
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ulmin(HME_BUFSZ, (d)->hrx_m->m_len - (sc)->sc_burst)
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struct hme_txdesc {
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struct mbuf *htx_m;
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bus_dmamap_t htx_dmamap;
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int htx_lastdesc;
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STAILQ_ENTRY(hme_txdesc) htx_q;
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};
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STAILQ_HEAD(hme_txdq, hme_txdesc);
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struct hme_ring {
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/* Ring Descriptors */
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caddr_t rb_membase; /* Packet buffer: CPU address */
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bus_addr_t rb_dmabase; /* Packet buffer: DMA address */
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caddr_t rb_txd; /* Transmit descriptors */
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bus_addr_t rb_txddma; /* DMA address of same */
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caddr_t rb_rxd; /* Receive descriptors */
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bus_addr_t rb_rxddma; /* DMA address of same */
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/* Ring Descriptor state */
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int rb_tdhead, rb_tdtail;
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int rb_rdtail;
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int rb_td_nbusy;
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/* Descriptors */
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struct hme_rxdesc rb_rxdesc[HME_NRXDESC];
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struct hme_txdesc rb_txdesc[HME_NTXQ];
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struct hme_txdq rb_txfreeq;
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struct hme_txdq rb_txbusyq;
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bus_dmamap_t rb_spare_dmamap;
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};
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struct hme_softc {
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struct ifnet *sc_ifp;
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struct ifmedia sc_ifmedia;
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device_t sc_dev;
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device_t sc_miibus;
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struct mii_data *sc_mii; /* MII media control */
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u_char sc_enaddr[ETHER_ADDR_LEN];
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struct callout sc_tick_ch; /* tick callout */
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int sc_wdog_timer; /* watchdog timer */
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/* The following bus handles are to be provided by the bus front-end */
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bus_dma_tag_t sc_pdmatag; /* bus dma parent tag */
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bus_dma_tag_t sc_cdmatag; /* control bus dma tag */
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bus_dmamap_t sc_cdmamap; /* control bus dma handle */
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bus_dma_tag_t sc_rdmatag; /* RX bus dma tag */
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bus_dma_tag_t sc_tdmatag; /* RX bus dma tag */
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bus_space_handle_t sc_sebh; /* HME Global registers */
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bus_space_handle_t sc_erxh; /* HME ERX registers */
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bus_space_handle_t sc_etxh; /* HME ETX registers */
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bus_space_handle_t sc_mach; /* HME MAC registers */
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bus_space_handle_t sc_mifh; /* HME MIF registers */
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bus_space_tag_t sc_sebt; /* HME Global registers */
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bus_space_tag_t sc_erxt; /* HME ERX registers */
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bus_space_tag_t sc_etxt; /* HME ETX registers */
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bus_space_tag_t sc_mact; /* HME MAC registers */
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bus_space_tag_t sc_mift; /* HME MIF registers */
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int sc_burst; /* DVMA burst size in effect */
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int sc_phys[2]; /* MII instance -> PHY map */
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u_int sc_flags;
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#define HME_LINK (1 << 0) /* link is up */
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#define HME_PCI (1 << 1) /* PCI busses are little-endian */
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int sc_ifflags;
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int sc_csum_features;
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/* Ring descriptor */
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struct hme_ring sc_rb;
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struct mtx sc_lock;
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};
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#define HME_LOCK(_sc) mtx_lock(&(_sc)->sc_lock)
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#define HME_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_lock)
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#define HME_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_lock, (_what))
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extern devclass_t hme_devclass;
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int hme_config(struct hme_softc *);
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void hme_detach(struct hme_softc *);
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void hme_suspend(struct hme_softc *);
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void hme_resume(struct hme_softc *);
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void hme_intr(void *);
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/* MII methods & callbacks */
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int hme_mii_readreg(device_t, int, int);
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int hme_mii_writereg(device_t, int, int, int);
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void hme_mii_statchg(device_t);
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