185 lines
6.1 KiB
C
185 lines
6.1 KiB
C
/*-
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* SPDX-License-Identifier: ISC
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*
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* Copyright (c) 2009 Rui Paulo <rpaulo@FreeBSD.org>
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* Copyright (c) 2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#ifndef _AH_EEPROM_V4K_H_
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#define _AH_EEPROM_V4K_H_
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#include "ah_eeprom.h"
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#include "ah_eeprom_v14.h"
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#if _BYTE_ORDER == _BIG_ENDIAN
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#define __BIG_ENDIAN_BITFIELD
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#endif
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#define AR9285_RDEXT_DEFAULT 0x1F
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#define AR5416_4K_EEP_PD_GAIN_BOUNDARY_DEFAULT 58
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#undef owl_eep_start_loc
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#ifdef __LINUX_ARM_ARCH__ /* AP71 */
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#define owl_eep_start_loc 0
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#else
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#define owl_eep_start_loc 64
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#endif
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// 16-bit offset location start of calibration struct
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#define AR5416_4K_EEP_START_LOC 64
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#define AR5416_4K_NUM_2G_CAL_PIERS 3
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#define AR5416_4K_NUM_2G_CCK_TARGET_POWERS 3
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#define AR5416_4K_NUM_2G_20_TARGET_POWERS 3
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#define AR5416_4K_NUM_2G_40_TARGET_POWERS 3
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#define AR5416_4K_NUM_CTLS 12
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#define AR5416_4K_NUM_BAND_EDGES 4
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#define AR5416_4K_NUM_PD_GAINS 2
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#define AR5416_4K_MAX_CHAINS 1
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/*
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* NB: The format in EEPROM has words 0 and 2 swapped (i.e. version
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* and length are swapped). We reverse their position after reading
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* the data into host memory so the version field is at the same
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* offset as in previous EEPROM layouts. This makes utilities that
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* inspect the EEPROM contents work without looking at the PCI device
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* id which may or may not be reliable.
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*/
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typedef struct BaseEepHeader4k {
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uint16_t version; /* NB: length in EEPROM */
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uint16_t checksum;
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uint16_t length; /* NB: version in EEPROM */
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uint8_t opCapFlags;
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uint8_t eepMisc;
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uint16_t regDmn[2];
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uint8_t macAddr[6];
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uint8_t rxMask;
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uint8_t txMask;
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uint16_t rfSilent;
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uint16_t blueToothOptions;
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uint16_t deviceCap;
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uint32_t binBuildNumber;
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uint8_t deviceType;
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uint8_t txGainType; /* high power tx gain table support */
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} __packed BASE_EEP4K_HEADER; // 32 B
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typedef struct ModalEepHeader4k {
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uint32_t antCtrlChain[AR5416_4K_MAX_CHAINS]; // 4
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uint32_t antCtrlCommon; // 4
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int8_t antennaGainCh[AR5416_4K_MAX_CHAINS]; // 1
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uint8_t switchSettling; // 1
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uint8_t txRxAttenCh[AR5416_4K_MAX_CHAINS]; // 1
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uint8_t rxTxMarginCh[AR5416_4K_MAX_CHAINS]; // 1
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uint8_t adcDesiredSize; // 1
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int8_t pgaDesiredSize; // 1
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uint8_t xlnaGainCh[AR5416_4K_MAX_CHAINS]; // 1
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uint8_t txEndToXpaOff; // 1
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uint8_t txEndToRxOn; // 1
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uint8_t txFrameToXpaOn; // 1
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uint8_t thresh62; // 1
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uint8_t noiseFloorThreshCh[AR5416_4K_MAX_CHAINS]; // 1
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uint8_t xpdGain; // 1
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uint8_t xpd; // 1
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int8_t iqCalICh[AR5416_4K_MAX_CHAINS]; // 1
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int8_t iqCalQCh[AR5416_4K_MAX_CHAINS]; // 1
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uint8_t pdGainOverlap; // 1
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#ifdef __BIG_ENDIAN_BITFIELD
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uint8_t ob_1:4, ob_0:4; // 1
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uint8_t db1_1:4, db1_0:4; // 1
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#else
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uint8_t ob_0:4, ob_1:4;
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uint8_t db1_0:4, db1_1:4;
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#endif
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uint8_t xpaBiasLvl; // 1
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uint8_t txFrameToDataStart; // 1
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uint8_t txFrameToPaOn; // 1
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uint8_t ht40PowerIncForPdadc; // 1
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uint8_t bswAtten[AR5416_4K_MAX_CHAINS]; // 1
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uint8_t bswMargin[AR5416_4K_MAX_CHAINS]; // 1
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uint8_t swSettleHt40; // 1
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uint8_t xatten2Db[AR5416_4K_MAX_CHAINS]; // 1
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uint8_t xatten2Margin[AR5416_4K_MAX_CHAINS]; // 1
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#ifdef __BIG_ENDIAN_BITFIELD
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uint8_t db2_1:4, db2_0:4; // 1
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#else
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uint8_t db2_0:4, db2_1:4; // 1
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#endif
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uint8_t version; // 1
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#ifdef __BIG_ENDIAN_BITFIELD
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uint8_t ob_3:4, ob_2:4; // 1
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uint8_t antdiv_ctl1:4, ob_4:4; // 1
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uint8_t db1_3:4, db1_2:4; // 1
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uint8_t antdiv_ctl2:4, db1_4:4; // 1
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uint8_t db2_2:4, db2_3:4; // 1
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uint8_t reserved:4, db2_4:4; // 1
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#else
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uint8_t ob_2:4, ob_3:4;
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uint8_t ob_4:4, antdiv_ctl1:4;
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uint8_t db1_2:4, db1_3:4;
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uint8_t db1_4:4, antdiv_ctl2:4;
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uint8_t db2_2:4, db2_3:4;
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uint8_t db2_4:4, reserved:4;
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#endif
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uint8_t tx_diversity;
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uint8_t flc_pwr_thresh;
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uint8_t bb_scale_smrt_antenna;
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#define EEP_4K_BB_DESIRED_SCALE_MASK 0x1f
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uint8_t futureModal[1];
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SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS]; // 20 B
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} __packed MODAL_EEP4K_HEADER; // == 68 B
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typedef struct CalCtlData4k {
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CAL_CTL_EDGES ctlEdges[AR5416_4K_MAX_CHAINS][AR5416_4K_NUM_BAND_EDGES];
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} __packed CAL_CTL_DATA_4K;
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typedef struct calDataPerFreq4k {
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uint8_t pwrPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
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uint8_t vpdPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
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} __packed CAL_DATA_PER_FREQ_4K;
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struct ar5416eeprom_4k {
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BASE_EEP4K_HEADER baseEepHeader; // 32 B
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uint8_t custData[20]; // 20 B
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MODAL_EEP4K_HEADER modalHeader; // 68 B
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uint8_t calFreqPier2G[AR5416_4K_NUM_2G_CAL_PIERS];
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CAL_DATA_PER_FREQ_4K calPierData2G[AR5416_4K_MAX_CHAINS][AR5416_4K_NUM_2G_CAL_PIERS];
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CAL_TARGET_POWER_LEG calTargetPowerCck[AR5416_4K_NUM_2G_CCK_TARGET_POWERS];
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CAL_TARGET_POWER_LEG calTargetPower2G[AR5416_4K_NUM_2G_20_TARGET_POWERS];
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CAL_TARGET_POWER_HT calTargetPower2GHT20[AR5416_4K_NUM_2G_20_TARGET_POWERS];
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CAL_TARGET_POWER_HT calTargetPower2GHT40[AR5416_4K_NUM_2G_40_TARGET_POWERS];
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uint8_t ctlIndex[AR5416_4K_NUM_CTLS];
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CAL_CTL_DATA_4K ctlData[AR5416_4K_NUM_CTLS];
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uint8_t padding;
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} __packed;
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typedef struct {
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struct ar5416eeprom_4k ee_base;
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#define NUM_EDGES 8
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uint16_t ee_numCtls;
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RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*AR5416_4K_NUM_CTLS];
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/* XXX these are dynamically calculated for use by shared code */
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int8_t ee_antennaGainMax;
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} HAL_EEPROM_v4k;
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#endif /* _AH_EEPROM_V4K_H_ */
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