638 lines
15 KiB
C
638 lines
15 KiB
C
/*
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* Copyright (c) 2000 Andrew Gallatin & Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Portions of this file were obtained from Compaq intellectual
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* property which was made available under the following copyright:
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*
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* *****************************************************************
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* * *
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* * Copyright Compaq Computer Corporation, 2000 *
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* * *
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* * Permission to use, copy, modify, distribute, and sell *
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* * this software and its documentation for any purpose is *
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* * hereby granted without fee, provided that the above *
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* * copyright notice appear in all copies and that both *
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* * that copyright notice and this permission notice appear *
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* * in supporting documentation, and that the name of *
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* * Compaq Computer Corporation not be used in advertising *
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* * or publicity pertaining to distribution of the software *
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* * without specific, written prior permission. Compaq *
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* * makes no representations about the suitability of this *
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* * software for any purpose. It is provided "AS IS" *
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* * without express or implied warranty. *
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* * *
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* *****************************************************************
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*/
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/*
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* T2 CBUS to PCI bridge
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/proc.h>
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#include <sys/rman.h>
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#include <sys/interrupt.h>
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#include <alpha/pci/t2reg.h>
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#include <alpha/pci/t2var.h>
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#include <alpha/isa/isavar.h>
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#include <machine/intr.h>
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#include <machine/resource.h>
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#include <machine/intrcnt.h>
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#include <machine/cpuconf.h>
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#include <machine/swiz.h>
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#include <machine/sgmap.h>
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#include <pci/pcivar.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa + sable_lynx_base)
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vm_offset_t sable_lynx_base = 0UL;
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volatile t2_csr_t *t2_csr[2];
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static int pci_int_type[2];
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static devclass_t t2_devclass;
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static device_t t2_0; /* XXX only one for now */
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struct t2_softc {
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int junk;
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};
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#define T2_SOFTC(dev) (struct t2_softc*) device_get_softc(dev)
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static alpha_chipset_read_hae_t t2_read_hae;
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static alpha_chipset_write_hae_t t2_write_hae;
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static alpha_chipset_t t2_chipset = {
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t2_read_hae,
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t2_write_hae,
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};
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static u_int32_t t2_hae_mem[2];
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#define REG1 (1UL << 24)
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static u_int32_t
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t2_set_hae_mem(void *arg, u_int32_t pa)
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{
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register_t s;
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u_int32_t msb;
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int hose;
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hose = (long)arg;
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if(pa >= REG1){
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msb = pa & 0xf8000000;
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pa -= msb;
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msb >>= 27; /* t2 puts high bits in the bottom of the register */
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s = intr_disable();
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if (msb != t2_hae_mem[hose]) {
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t2_hae_mem[hose] = msb;
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t2_csr[hose]->hae0_1 = t2_hae_mem[hose];
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alpha_mb();
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t2_hae_mem[hose] = t2_csr[hose]->hae0_1;
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}
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intr_restore(s);
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}
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return pa;
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}
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static u_int64_t
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t2_read_hae(void)
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{
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return t2_hae_mem[0] << 27;
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}
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static void
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t2_write_hae(u_int64_t hae)
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{
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u_int32_t pa = hae;
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t2_set_hae_mem(0, pa);
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}
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static int t2_probe(device_t dev);
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static int t2_attach(device_t dev);
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static int t2_setup_intr(device_t dev, device_t child,
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struct resource *irq, int flags,
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void *intr, void *arg, void **cookiep);
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static int t2_teardown_intr(device_t dev, device_t child,
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struct resource *irq, void *cookie);
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static void
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t2_dispatch_intr(void *frame, unsigned long vector);
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static void
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t2_machine_check(unsigned long mces, struct trapframe *framep,
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unsigned long vector, unsigned long param);
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static device_method_t t2_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, t2_probe),
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DEVMETHOD(device_attach, t2_attach),
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/* Bus interface */
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DEVMETHOD(bus_setup_intr, t2_setup_intr),
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DEVMETHOD(bus_teardown_intr, t2_teardown_intr),
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{ 0, 0 }
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};
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static driver_t t2_driver = {
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"t2",
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t2_methods,
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sizeof(struct t2_softc),
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};
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#define T2_SGMAP_BASE (8*1024*1024)
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#define T2_SGMAP_SIZE (8*1024*1024)
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static void
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t2_sgmap_invalidate(void)
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{
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u_int64_t val;
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alpha_mb();
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val = REGVAL64(T2_IOCSR);
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val |= T2_IOCSRL_ITLB;
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REGVAL64(T2_IOCSR) = val;
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alpha_mb();
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alpha_mb();
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val = REGVAL64(T2_IOCSR);
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val &= ~T2_IOCSRL_ITLB;
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REGVAL64(T2_IOCSR) = val;
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alpha_mb();
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alpha_mb();
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}
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static void
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t2_sgmap_map(void *arg, bus_addr_t ba, vm_offset_t pa)
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{
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u_int64_t *sgtable = arg;
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int index = alpha_btop(ba - T2_SGMAP_BASE);
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if (pa) {
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if (pa > (1L<<32))
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panic("t2_sgmap_map: can't map address 0x%lx", pa);
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sgtable[index] = ((pa >> 13) << 1) | 1;
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} else {
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sgtable[index] = 0;
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}
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alpha_mb();
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t2_sgmap_invalidate();
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}
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static void
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t2_init_sgmap(int h)
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{
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void *sgtable;
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/*
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* First setup Window 2 to map 8Mb to 16Mb with an
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* sgmap. Allocate the map aligned to a 32 boundary.
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*
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* bits 31..20 of WBASE represent the pci start address
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* (in units of 1Mb), and bits 11..0 represent the pci
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* end address
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*/
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t2_csr[h]->wbase2 = T2_WSIZE_8M|T2_WINDOW_ENABLE|T2_WINDOW_SG
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| ((T2_SGMAP_BASE >> 20) << 20)
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| ((T2_SGMAP_BASE + T2_SGMAP_SIZE) >> 20);
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t2_csr[h]->wmask2 = T2_WMASK_8M;
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alpha_mb();
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sgtable = contigmalloc(8192, M_DEVBUF, M_NOWAIT,
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0, (1L<<34),
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32*1024, (1L<<34));
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if (!sgtable)
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panic("t2_init_sgmap: can't allocate page table");
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t2_csr[h]->tbase2 =
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(pmap_kextract((vm_offset_t) sgtable) >> T2_TBASE_SHIFT);
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chipset.sgmap = sgmap_map_create(T2_SGMAP_BASE,
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T2_SGMAP_BASE + T2_SGMAP_SIZE,
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t2_sgmap_map, sgtable);
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}
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static void
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t2_csr_init(int h)
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{
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/*
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* initialize the DMA windows
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*/
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t2_csr[h]->wbase1 = T2_WSIZE_1G|T2_WINDOW_ENABLE|T2_WINDOW_DIRECT|0x7ff;
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t2_csr[h]->wmask1 = T2_WMASK_1G;
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t2_csr[h]->tbase1 = 0x0;
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t2_csr[h]->wbase2 = 0x0;
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/*
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* enable the PCI "Hole" for ISA devices which use memory in
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* the 512k - 1MB range
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*/
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t2_csr[h]->hbase = 1 << 13;
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t2_init_sgmap(0);
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/* initialize the HAEs */
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t2_csr[h]->hae0_1 = 0x0;
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alpha_mb();
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t2_csr[h]->hae0_2 = 0x0;
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alpha_mb();
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t2_csr[h]->hae0_3 = 0x0;
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alpha_mb();
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}
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/*
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* Perform basic chipset init/fixup. Called by various early
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* consumers to ensure that the system will work before the
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* bus methods are invoked.
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*
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*/
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void
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t2_init()
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{
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static int initted = 0;
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static struct swiz_space io_space, mem_space;
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if (initted) return;
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initted = 1;
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swiz_init_space(&io_space, KV(T2_PCI_SIO));
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swiz_init_space_hae(&mem_space, KV(T2_PCI_SPARSE),
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t2_set_hae_mem, 0);
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busspace_isa_io = (struct alpha_busspace *) &io_space;
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busspace_isa_mem = (struct alpha_busspace *) &mem_space;
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chipset = t2_chipset;
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}
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static int
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t2_probe(device_t dev)
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{
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int h, t2_num_hoses = 1;
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device_t child;
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if (t2_0)
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return ENXIO;
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t2_0 = dev;
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device_set_desc(dev, "T2 Core Logic chipset");
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t2_csr[0] = (t2_csr_t *)
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ALPHA_PHYS_TO_K0SEG(sable_lynx_base + PCI0_BASE);
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t2_csr[1] = (t2_csr_t *)
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ALPHA_PHYS_TO_K0SEG(sable_lynx_base + PCI1_BASE);
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/* Look at the rev of the chip. If the high bit is set in the
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* rev field then we have either a T3 or a T4 chip, so use the
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* new interrupt structure. If it is clear, then we have a T2
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* so use the old way */
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platform.mcheck_handler = t2_machine_check;
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if (((t2_csr[0]->iocsr) >> 35) & 1)
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pci_int_type[0] = 1;
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else
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pci_int_type[0] = 0;
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device_printf(dev, "using interrupt type %d on pci bus 0\n",
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pci_int_type[0]);
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if (!badaddr(__DEVOLATILE(void *, &t2_csr[1]->tlbbr), sizeof(long))) {
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pci_int_type[1] = 1; /* PCI1 always uses the new scheme */
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/* Clear any errors that the BADADDR probe may have caused */
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t2_csr[1]->cerr1 |= t2_csr[1]->cerr1;
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t2_csr[1]->pcierr1 |= t2_csr[1]->pcierr1;
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device_printf(dev, "found EXT_IO!!!!!\n");
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/* t2_num_hoses = 2; XXX not ready for this yet */
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}
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for (h = 0; h < t2_num_hoses; h++)
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t2_csr_init(h);
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child = device_add_child(dev, "pcib", 0);
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device_set_ivars(child, 0);
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return 0;
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}
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static int
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t2_attach(device_t dev)
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{
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t2_init();
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set_iointr(t2_dispatch_intr);
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platform.isa_setup_intr = t2_setup_intr;
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platform.isa_teardown_intr = t2_teardown_intr;
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snprintf(chipset_type, sizeof(chipset_type), "t2");
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bus_generic_attach(dev);
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return 0;
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}
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/*
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* magical mystery table partly obtained from Linux
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* at least some of their values for PCI masks
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* were incorrect, and I've filled in my own extrapolations
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* XXX this needs more testers
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*/
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unsigned long t2_shadow_mask = -1L;
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static const char irq_to_mask[40] = {
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-1, 6, -1, 8, 15, 12, 7, 9, /* ISA 0-7 */
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-1, 16, 17, 18, 3, -1, 21, 22, /* ISA 8-15 */
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-1, -1, -1, -1, -1, -1, -1, -1, /* ?? EISA XXX */
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-1, -1, -1, -1, -1, -1, -1, -1, /* ?? EISA XXX */
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0, 1, 2, 3, 4, 5, 6, 7 /* PCI 0-7 XXX */
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};
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static void
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t2_8259_disable_mask(int mask)
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{
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t2_shadow_mask |= (1UL << mask);
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if (mask <= 7)
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outb(SLAVE0_ICU, t2_shadow_mask);
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else if (mask <= 15)
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outb(SLAVE1_ICU, t2_shadow_mask >> 8);
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else
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outb(SLAVE2_ICU, t2_shadow_mask >> 16);
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}
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static void
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t2_8259_enable_mask(int mask)
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{
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t2_shadow_mask &= ~(1UL << mask);
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if (mask <= 7)
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outb(SLAVE0_ICU, t2_shadow_mask);
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else if (mask <= 15)
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outb(SLAVE1_ICU, t2_shadow_mask >> 8);
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else
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outb(SLAVE2_ICU, t2_shadow_mask >> 16);
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}
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static void
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t2_eoi( int vector)
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{
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int irq, hose;
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hose = (vector >= 0xC00);
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irq = (vector - 0x800) >> 4;
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if (pci_int_type[hose]) {
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/* New interrupt scheme. Both PCI0 and PCI1 can use
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* the same handler. Dispatching interrupts with the
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* IC IC chip is easy. We simply write the vector
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* address register (var) on the T3/T4 (offset
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* 0x480) with the IRQ level (0 - 63) of what came in. */
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t2_csr[hose]->var = (u_long) irq;
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alpha_mb();
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alpha_mb();
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} else {
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switch (irq) {
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case 0 ... 7:
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outb(SLAVE0_ICU-1, (0xe0 | (irq)));
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outb(MASTER_ICU-1, (0xe0 | 1));
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break;
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case 8 ... 15:
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outb(SLAVE1_ICU-1, (0xe0 | (irq - 8)));
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outb(MASTER_ICU-1, (0xe0 | 3));
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break;
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case 16 ... 24:
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outb(SLAVE2_ICU-1, (0xe0 | (irq - 16)));
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outb(MASTER_ICU-1, (0xe0 | 4));
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break;
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}
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}
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}
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static void
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t2_enable_vec(int vector)
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{
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int irq, hose;
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u_long IC_mask, scratch;
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hose = (vector >= 0xC00);
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irq = (vector - 0x800) >> 4;
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mtx_lock_spin(&icu_lock);
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if (pci_int_type[hose]) {
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/* Write the air register on the T3/T4 with the
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* address of the IC IC masks register (offset 0x40) */
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t2_csr[hose]->air = 0x40;
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alpha_mb();
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scratch = t2_csr[hose]->air;
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alpha_mb();
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IC_mask = t2_csr[hose]->dir;
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IC_mask &= ~(1L << ( (u_long) irq));
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t2_csr[hose]->dir = IC_mask;
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alpha_mb();
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alpha_mb();
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/*
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* EOI the interrupt we just enabled.
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*/
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t2_eoi(vector);
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} else {
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/* Old style 8259 (Gack!!!) interrupts */
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t2_8259_enable_mask(irq);
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}
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mtx_unlock_spin(&icu_lock);
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}
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static void
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t2_disable_vec(int vector)
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{
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int hose, irq;
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u_long scratch, IC_mask;
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hose = (vector >= 0xC00);
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irq = (vector - 0x800) >> 4;
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mtx_lock_spin(&icu_lock);
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if (pci_int_type[hose]) {
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/* Write the air register on the T3/T4 wioth the
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* address of the IC IC masks register (offset 0x40) */
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t2_csr[hose]->air = 0x40;
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alpha_mb();
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scratch = t2_csr[hose]->air;
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alpha_mb();
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/*
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|
* Read the dir register to fetch the mask data, 'or' in the
|
|
* new disable bit, and write the data back.
|
|
*/
|
|
IC_mask = t2_csr[hose]->dir;
|
|
IC_mask |= (1L << ( (u_long) irq));
|
|
/* Set the disable bit */
|
|
t2_csr[hose]->dir = IC_mask;
|
|
alpha_mb();
|
|
alpha_mb();
|
|
} else {
|
|
/* Old style 8259 (Gack!!!) interrupts */
|
|
t2_8259_disable_mask(irq);
|
|
}
|
|
mtx_unlock_spin(&icu_lock);
|
|
}
|
|
|
|
|
|
static int
|
|
t2_setup_intr(device_t dev, device_t child,
|
|
struct resource *irq, int flags,
|
|
void *intr, void *arg, void **cookiep)
|
|
{
|
|
int error, vector, stdio_irq;
|
|
const char *name;
|
|
device_t bus, parent;
|
|
|
|
name = device_get_nameunit(dev);
|
|
stdio_irq = irq->r_start;
|
|
if (strncmp(name, "eisa", 4) == 0) {
|
|
if ((stdio_irq != 6 ) && (stdio_irq != 3 )) {
|
|
stdio_irq =
|
|
T2_EISA_IRQ_TO_STDIO_IRQ(stdio_irq);
|
|
}
|
|
} else if ((strncmp(name, "isa", 3)) == 0) {
|
|
stdio_irq = irq_to_mask[stdio_irq];
|
|
}
|
|
|
|
parent = dev;
|
|
do {
|
|
bus = parent;
|
|
parent = device_get_parent(bus);
|
|
} while (parent && strncmp("t2", device_get_nameunit(parent), 2));
|
|
|
|
if (parent && (device_get_unit(bus) != 0))
|
|
vector = STDIO_PCI1_IRQ_TO_SCB_VECTOR(stdio_irq);
|
|
else
|
|
vector = STDIO_PCI0_IRQ_TO_SCB_VECTOR(stdio_irq);
|
|
|
|
error = rman_activate_resource(irq);
|
|
if (error)
|
|
return error;
|
|
|
|
error = alpha_setup_intr(device_get_nameunit(child ? child : dev),
|
|
vector, intr, arg, flags, cookiep,
|
|
&intrcnt[irq->r_start], t2_disable_vec, t2_enable_vec);
|
|
|
|
if (error)
|
|
return error;
|
|
|
|
/* Enable interrupt */
|
|
t2_enable_vec(vector);
|
|
|
|
if (bootverbose != 0)
|
|
device_printf(child,
|
|
"interrupting at T2 irq %d (stdio irq %d)\n",
|
|
(int) irq->r_start, stdio_irq);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
t2_teardown_intr(device_t dev, device_t child,
|
|
struct resource *irq, void *cookie)
|
|
{
|
|
int mask;
|
|
|
|
mask = irq_to_mask[irq->r_start];
|
|
|
|
/* Disable interrupt */
|
|
|
|
/*
|
|
* XXX this is totally broken!
|
|
* we don't have enough info to figure out where the interrupt
|
|
* came from if hose != 0 and pci_int_type[hose] != 0
|
|
* We should probably carry around the vector someplace --
|
|
* that would be enough to figure out the hose and the stdio irq
|
|
*/
|
|
|
|
t2_shadow_mask |= (1UL << mask);
|
|
|
|
mtx_lock_spin(&icu_lock);
|
|
if (mask <= 7)
|
|
outb(SLAVE0_ICU, t2_shadow_mask);
|
|
else if (mask <= 15)
|
|
outb(SLAVE1_ICU, t2_shadow_mask >> 8);
|
|
else
|
|
outb(SLAVE2_ICU, t2_shadow_mask >> 16);
|
|
mtx_unlock_spin(&icu_lock);
|
|
|
|
alpha_teardown_intr(cookie);
|
|
return rman_deactivate_resource(irq);
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
t2_dispatch_intr(void *frame, unsigned long vector)
|
|
{
|
|
alpha_dispatch_intr(frame, vector);
|
|
mtx_lock_spin(&icu_lock);
|
|
t2_eoi(vector);
|
|
mtx_unlock_spin(&icu_lock);
|
|
}
|
|
|
|
static void
|
|
t2_machine_check(unsigned long mces, struct trapframe *framep,
|
|
unsigned long vector, unsigned long param)
|
|
{
|
|
int expected;
|
|
|
|
expected = mc_expected;
|
|
machine_check(mces, framep, vector, param);
|
|
/* for some reason the alpha_pal_wrmces() doesn't clear all
|
|
pending machine checks & we may take another */
|
|
mc_expected = expected;
|
|
}
|
|
|
|
DRIVER_MODULE(t2, root, t2_driver, t2_devclass, 0, 0);
|