dc4ee6ca91
make use of it where possible. This primarily brings in support for newer hardware, and FreeBSD is not yet able to support the abundance of IRQs on new hardware and many features in the Ethernet driver. Because of the changes to IRQs in the Simple Executive, we have to maintain our own list of Octeon IRQs now, which probably can be pared-down and be specific to the CIU interrupt unit soon, and when other interrupt mechanisms are added they can maintain their own definitions. Remove unmasking of interrupts from within the UART device now that the function used is no longer present in the Simple Executive. The unmasking seems to have been gratuitous as this is more properly handled by the buses above the UART device, and seems to work on that basis.
605 lines
20 KiB
C
605 lines
20 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* Interface to the hardware Fetch and Add Unit.
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*
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* <hr>$Revision: 70030 $<hr>
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*/
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#ifndef __CVMX_FAU_H__
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#define __CVMX_FAU_H__
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#ifndef CVMX_DONT_INCLUDE_CONFIG
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#include "cvmx-config.h"
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#else
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typedef int cvmx_fau_reg_64_t;
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typedef int cvmx_fau_reg_32_t;
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typedef int cvmx_fau_reg_16_t;
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typedef int cvmx_fau_reg_8_t;
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Octeon Fetch and Add Unit (FAU)
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*/
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#define CVMX_FAU_LOAD_IO_ADDRESS cvmx_build_io_address(0x1e, 0)
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#define CVMX_FAU_BITS_SCRADDR 63,56
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#define CVMX_FAU_BITS_LEN 55,48
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#define CVMX_FAU_BITS_INEVAL 35,14
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#define CVMX_FAU_BITS_TAGWAIT 13,13
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#define CVMX_FAU_BITS_NOADD 13,13
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#define CVMX_FAU_BITS_SIZE 12,11
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#define CVMX_FAU_BITS_REGISTER 10,0
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typedef enum {
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CVMX_FAU_OP_SIZE_8 = 0,
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CVMX_FAU_OP_SIZE_16 = 1,
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CVMX_FAU_OP_SIZE_32 = 2,
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CVMX_FAU_OP_SIZE_64 = 3
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} cvmx_fau_op_size_t;
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/**
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* Tagwait return definition. If a timeout occurs, the error
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* bit will be set. Otherwise the value of the register before
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* the update will be returned.
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*/
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typedef struct
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{
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uint64_t error : 1;
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int64_t value : 63;
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} cvmx_fau_tagwait64_t;
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/**
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* Tagwait return definition. If a timeout occurs, the error
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* bit will be set. Otherwise the value of the register before
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* the update will be returned.
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*/
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typedef struct
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{
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uint64_t error : 1;
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int32_t value : 31;
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} cvmx_fau_tagwait32_t;
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/**
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* Tagwait return definition. If a timeout occurs, the error
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* bit will be set. Otherwise the value of the register before
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* the update will be returned.
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*/
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typedef struct
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{
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uint64_t error : 1;
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int16_t value : 15;
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} cvmx_fau_tagwait16_t;
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/**
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* Tagwait return definition. If a timeout occurs, the error
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* bit will be set. Otherwise the value of the register before
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* the update will be returned.
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*/
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typedef struct
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{
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uint64_t error : 1;
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int8_t value : 7;
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} cvmx_fau_tagwait8_t;
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/**
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* Asynchronous tagwait return definition. If a timeout occurs,
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* the error bit will be set. Otherwise the value of the
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* register before the update will be returned.
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*/
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typedef union {
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uint64_t u64;
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struct {
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uint64_t invalid: 1;
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uint64_t data :63; /* unpredictable if invalid is set */
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} s;
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} cvmx_fau_async_tagwait_result_t;
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/**
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* @INTERNAL
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* Builds a store I/O address for writing to the FAU
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*
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* @param noadd 0 = Store value is atomically added to the current value
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* 1 = Store value is atomically written over the current value
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 2 for 16 bit access.
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* - Step by 4 for 32 bit access.
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* - Step by 8 for 64 bit access.
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* @return Address to store for atomic update
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*/
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static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg)
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{
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return (CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
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cvmx_build_bits(CVMX_FAU_BITS_NOADD, noadd) |
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cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg));
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}
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/**
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* @INTERNAL
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* Builds a I/O address for accessing the FAU
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*
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* @param tagwait Should the atomic add wait for the current tag switch
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* operation to complete.
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* - 0 = Don't wait
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* - 1 = Wait for tag switch to complete
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 2 for 16 bit access.
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* - Step by 4 for 32 bit access.
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* - Step by 8 for 64 bit access.
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* @param value Signed value to add.
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* Note: When performing 32 and 64 bit access, only the low
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* 22 bits are available.
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* @return Address to read from for atomic update
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*/
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static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg, int64_t value)
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{
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return (CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
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cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) |
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cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) |
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cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg));
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}
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/**
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* Perform an atomic 64 bit add
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 8 for 64 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Value of the register before the update
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*/
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static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value)
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{
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return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value));
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}
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/**
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* Perform an atomic 32 bit add
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 4 for 32 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Value of the register before the update
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*/
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static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value)
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{
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return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value));
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}
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/**
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* Perform an atomic 16 bit add
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 2 for 16 bit access.
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* @param value Signed value to add.
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* @return Value of the register before the update
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*/
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static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value)
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{
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return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value));
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}
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/**
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* Perform an atomic 8 bit add
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* @param value Signed value to add.
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* @return Value of the register before the update
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*/
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static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
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{
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return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value));
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}
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/**
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* Perform an atomic 64 bit add after the current tag switch
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* completes
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 8 for 64 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return If a timeout occurs, the error bit will be set. Otherwise
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* the value of the register before the update will be
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* returned
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*/
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static inline cvmx_fau_tagwait64_t cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value)
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{
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union
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{
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uint64_t i64;
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cvmx_fau_tagwait64_t t;
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} result;
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result.i64 = cvmx_read64_int64(__cvmx_fau_atomic_address(1, reg, value));
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return result.t;
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}
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/**
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* Perform an atomic 32 bit add after the current tag switch
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* completes
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 4 for 32 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return If a timeout occurs, the error bit will be set. Otherwise
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* the value of the register before the update will be
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* returned
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*/
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static inline cvmx_fau_tagwait32_t cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value)
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{
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union
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{
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uint64_t i32;
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cvmx_fau_tagwait32_t t;
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} result;
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result.i32 = cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value));
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return result.t;
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}
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/**
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* Perform an atomic 16 bit add after the current tag switch
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* completes
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 2 for 16 bit access.
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* @param value Signed value to add.
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* @return If a timeout occurs, the error bit will be set. Otherwise
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* the value of the register before the update will be
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* returned
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*/
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static inline cvmx_fau_tagwait16_t cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value)
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{
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union
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{
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uint64_t i16;
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cvmx_fau_tagwait16_t t;
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} result;
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result.i16 = cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value));
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return result.t;
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}
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/**
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* Perform an atomic 8 bit add after the current tag switch
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* completes
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*
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* @param value Signed value to add.
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* @return If a timeout occurs, the error bit will be set. Otherwise
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* the value of the register before the update will be
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* returned
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*/
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static inline cvmx_fau_tagwait8_t cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
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{
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union
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{
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uint64_t i8;
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cvmx_fau_tagwait8_t t;
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} result;
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result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value));
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return result.t;
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}
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/**
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* @INTERNAL
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* Builds I/O data for async operations
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*
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* @param scraddr Scratch pad byte addres to write to. Must be 8 byte aligned
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* @param value Signed value to add.
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* Note: When performing 32 and 64 bit access, only the low
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* 22 bits are available.
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* @param tagwait Should the atomic add wait for the current tag switch
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* operation to complete.
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* - 0 = Don't wait
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* - 1 = Wait for tag switch to complete
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* @param size The size of the operation:
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* - CVMX_FAU_OP_SIZE_8 (0) = 8 bits
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* - CVMX_FAU_OP_SIZE_16 (1) = 16 bits
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* - CVMX_FAU_OP_SIZE_32 (2) = 32 bits
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* - CVMX_FAU_OP_SIZE_64 (3) = 64 bits
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 2 for 16 bit access.
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* - Step by 4 for 32 bit access.
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* - Step by 8 for 64 bit access.
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* @return Data to write using cvmx_send_single
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*/
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static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value, uint64_t tagwait,
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cvmx_fau_op_size_t size, uint64_t reg)
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{
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return (CVMX_FAU_LOAD_IO_ADDRESS |
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cvmx_build_bits(CVMX_FAU_BITS_SCRADDR, scraddr>>3) |
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cvmx_build_bits(CVMX_FAU_BITS_LEN, 1) |
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cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) |
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cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) |
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cvmx_build_bits(CVMX_FAU_BITS_SIZE, size) |
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cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg));
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}
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/**
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* Perform an async atomic 64 bit add. The old value is
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* placed in the scratch memory at byte address scraddr.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 8 for 64 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Placed in the scratch pad register
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*/
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static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr, cvmx_fau_reg_64_t reg, int64_t value)
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{
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cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg));
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}
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/**
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* Perform an async atomic 32 bit add. The old value is
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* placed in the scratch memory at byte address scraddr.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 4 for 32 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Placed in the scratch pad register
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*/
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static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr, cvmx_fau_reg_32_t reg, int32_t value)
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{
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cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg));
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}
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/**
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* Perform an async atomic 16 bit add. The old value is
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* placed in the scratch memory at byte address scraddr.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 2 for 16 bit access.
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* @param value Signed value to add.
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* @return Placed in the scratch pad register
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*/
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static inline void cvmx_fau_async_fetch_and_add16(uint64_t scraddr, cvmx_fau_reg_16_t reg, int16_t value)
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{
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cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg));
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}
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/**
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* Perform an async atomic 8 bit add. The old value is
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* placed in the scratch memory at byte address scraddr.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* @param value Signed value to add.
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* @return Placed in the scratch pad register
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*/
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static inline void cvmx_fau_async_fetch_and_add8(uint64_t scraddr, cvmx_fau_reg_8_t reg, int8_t value)
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{
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cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg));
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}
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/**
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* Perform an async atomic 64 bit add after the current tag
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* switch completes.
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*
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* If a timeout occurs, the error bit (63) will be set. Otherwise
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* the value of the register before the update will be
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* returned
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 8 for 64 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Placed in the scratch pad register
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*/
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static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr, cvmx_fau_reg_64_t reg, int64_t value)
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{
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cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg));
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}
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/**
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* Perform an async atomic 32 bit add after the current tag
|
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* switch completes.
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*
|
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* @param scraddr Scratch memory byte address to put response in.
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* Must be 8 byte aligned.
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* If a timeout occurs, the error bit (63) will be set. Otherwise
|
|
* the value of the register before the update will be
|
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* returned
|
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* @param reg FAU atomic register to access. 0 <= reg < 2048.
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* - Step by 4 for 32 bit access.
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* @param value Signed value to add.
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* Note: Only the low 22 bits are available.
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* @return Placed in the scratch pad register
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*/
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static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr, cvmx_fau_reg_32_t reg, int32_t value)
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{
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cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg));
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}
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/**
|
|
* Perform an async atomic 16 bit add after the current tag
|
|
* switch completes.
|
|
*
|
|
* @param scraddr Scratch memory byte address to put response in.
|
|
* Must be 8 byte aligned.
|
|
* If a timeout occurs, the error bit (63) will be set. Otherwise
|
|
* the value of the register before the update will be
|
|
* returned
|
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
|
* - Step by 2 for 16 bit access.
|
|
* @param value Signed value to add.
|
|
* @return Placed in the scratch pad register
|
|
*/
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static inline void cvmx_fau_async_tagwait_fetch_and_add16(uint64_t scraddr, cvmx_fau_reg_16_t reg, int16_t value)
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{
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cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg));
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}
|
|
|
|
/**
|
|
* Perform an async atomic 8 bit add after the current tag
|
|
* switch completes.
|
|
*
|
|
* @param scraddr Scratch memory byte address to put response in.
|
|
* Must be 8 byte aligned.
|
|
* If a timeout occurs, the error bit (63) will be set. Otherwise
|
|
* the value of the register before the update will be
|
|
* returned
|
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
|
* @param value Signed value to add.
|
|
* @return Placed in the scratch pad register
|
|
*/
|
|
static inline void cvmx_fau_async_tagwait_fetch_and_add8(uint64_t scraddr, cvmx_fau_reg_8_t reg, int8_t value)
|
|
{
|
|
cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg));
|
|
}
|
|
|
|
/**
|
|
* Perform an atomic 64 bit add
|
|
*
|
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
|
* - Step by 8 for 64 bit access.
|
|
* @param value Signed value to add.
|
|
*/
|
|
static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value)
|
|
{
|
|
cvmx_write64_int64(__cvmx_fau_store_address(0, reg), value);
|
|
}
|
|
|
|
/**
|
|
* Perform an atomic 32 bit add
|
|
*
|
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
|
* - Step by 4 for 32 bit access.
|
|
* @param value Signed value to add.
|
|
*/
|
|
static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value)
|
|
{
|
|
cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value);
|
|
}
|
|
|
|
/**
|
|
* Perform an atomic 16 bit add
|
|
*
|
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
|
* - Step by 2 for 16 bit access.
|
|
* @param value Signed value to add.
|
|
*/
|
|
static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value)
|
|
{
|
|
cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value);
|
|
}
|
|
|
|
/**
|
|
* Perform an atomic 8 bit add
|
|
*
|
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
|
* @param value Signed value to add.
|
|
*/
|
|
static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value)
|
|
{
|
|
cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value);
|
|
}
|
|
|
|
/**
|
|
* Perform an atomic 64 bit write
|
|
*
|
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
|
* - Step by 8 for 64 bit access.
|
|
* @param value Signed value to write.
|
|
*/
|
|
static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value)
|
|
{
|
|
cvmx_write64_int64(__cvmx_fau_store_address(1, reg), value);
|
|
}
|
|
|
|
/**
|
|
* Perform an atomic 32 bit write
|
|
*
|
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
|
* - Step by 4 for 32 bit access.
|
|
* @param value Signed value to write.
|
|
*/
|
|
static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value)
|
|
{
|
|
cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value);
|
|
}
|
|
|
|
/**
|
|
* Perform an atomic 16 bit write
|
|
*
|
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
|
* - Step by 2 for 16 bit access.
|
|
* @param value Signed value to write.
|
|
*/
|
|
static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value)
|
|
{
|
|
cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value);
|
|
}
|
|
|
|
/**
|
|
* Perform an atomic 8 bit write
|
|
*
|
|
* @param reg FAU atomic register to access. 0 <= reg < 2048.
|
|
* @param value Signed value to write.
|
|
*/
|
|
static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value)
|
|
{
|
|
cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value);
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __CVMX_FAU_H__ */
|