04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
148 lines
5.2 KiB
C
148 lines
5.2 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* cvmx-asx0-defs.h
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*
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* Configuration and status register (CSR) type definitions for
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* Octeon asx0.
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*
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* This file is auto generated. Do not edit.
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*
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* <hr>$Revision$<hr>
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*
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*/
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#ifndef __CVMX_ASX0_TYPEDEFS_H__
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#define __CVMX_ASX0_TYPEDEFS_H__
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_ASX0_DBG_DATA_DRV CVMX_ASX0_DBG_DATA_DRV_FUNC()
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static inline uint64_t CVMX_ASX0_DBG_DATA_DRV_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
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cvmx_warn("CVMX_ASX0_DBG_DATA_DRV not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x00011800B0000208ull);
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}
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#else
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#define CVMX_ASX0_DBG_DATA_DRV (CVMX_ADD_IO_SEG(0x00011800B0000208ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_ASX0_DBG_DATA_ENABLE CVMX_ASX0_DBG_DATA_ENABLE_FUNC()
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static inline uint64_t CVMX_ASX0_DBG_DATA_ENABLE_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
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cvmx_warn("CVMX_ASX0_DBG_DATA_ENABLE not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x00011800B0000200ull);
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}
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#else
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#define CVMX_ASX0_DBG_DATA_ENABLE (CVMX_ADD_IO_SEG(0x00011800B0000200ull))
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#endif
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/**
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* cvmx_asx0_dbg_data_drv
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*
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* ASX_DBG_DATA_DRV
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*
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*/
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union cvmx_asx0_dbg_data_drv
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{
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uint64_t u64;
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struct cvmx_asx0_dbg_data_drv_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_9_63 : 55;
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uint64_t pctl : 5; /**< These bits control the driving strength of the dbg
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interface. */
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uint64_t nctl : 4; /**< These bits control the driving strength of the dbg
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interface. */
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#else
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uint64_t nctl : 4;
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uint64_t pctl : 5;
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uint64_t reserved_9_63 : 55;
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#endif
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} s;
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struct cvmx_asx0_dbg_data_drv_cn38xx
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_8_63 : 56;
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uint64_t pctl : 4; /**< These bits control the driving strength of the dbg
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interface. */
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uint64_t nctl : 4; /**< These bits control the driving strength of the dbg
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interface. */
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#else
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uint64_t nctl : 4;
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uint64_t pctl : 4;
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uint64_t reserved_8_63 : 56;
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#endif
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} cn38xx;
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struct cvmx_asx0_dbg_data_drv_cn38xx cn38xxp2;
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struct cvmx_asx0_dbg_data_drv_s cn58xx;
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struct cvmx_asx0_dbg_data_drv_s cn58xxp1;
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};
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typedef union cvmx_asx0_dbg_data_drv cvmx_asx0_dbg_data_drv_t;
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/**
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* cvmx_asx0_dbg_data_enable
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*
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* ASX_DBG_DATA_ENABLE
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*
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*/
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union cvmx_asx0_dbg_data_enable
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{
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uint64_t u64;
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struct cvmx_asx0_dbg_data_enable_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_1_63 : 63;
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uint64_t en : 1; /**< A 1->0 transistion, turns the dbg interface OFF. */
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#else
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uint64_t en : 1;
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uint64_t reserved_1_63 : 63;
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#endif
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} s;
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struct cvmx_asx0_dbg_data_enable_s cn38xx;
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struct cvmx_asx0_dbg_data_enable_s cn38xxp2;
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struct cvmx_asx0_dbg_data_enable_s cn58xx;
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struct cvmx_asx0_dbg_data_enable_s cn58xxp1;
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};
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typedef union cvmx_asx0_dbg_data_enable cvmx_asx0_dbg_data_enable_t;
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#endif
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