427 lines
11 KiB
C
427 lines
11 KiB
C
/*-
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* Copyright (c) 2003-2009 RMI Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of RMI Corporation, nor the names of its contributors,
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RMI_BSD */
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/types.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <machine/md_var.h>
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#include <mips/rmi/rmi_mips_exts.h>
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#include <machine/cpuregs.h>
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/pmap.h>
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#include <sys/rman.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include <mips/rmi/iomap.h>
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#include <mips/rmi/pic.h>
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#include <mips/rmi/shared_structs.h>
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#include <mips/rmi/board.h>
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#include <mips/rmi/pcibus.h>
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#include "pcib_if.h"
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#define LSU_CFG0_REGID 0
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#define LSU_CERRLOG_REGID 9
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#define LSU_CERROVF_REGID 10
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#define LSU_CERRINT_REGID 11
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#define SWAP32(x)\
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(((x) & 0xff000000) >> 24) | \
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(((x) & 0x000000ff) << 24) | \
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(((x) & 0x0000ff00) << 8) | \
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(((x) & 0x00ff0000) >> 8)
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/* MSI support */
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#define MSI_MIPS_ADDR_DEST 0x000ff000
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#define MSI_MIPS_ADDR_RH 0x00000008
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#define MSI_MIPS_ADDR_RH_OFF 0x00000000
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#define MSI_MIPS_ADDR_RH_ON 0x00000008
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#define MSI_MIPS_ADDR_DM 0x00000004
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#define MSI_MIPS_ADDR_DM_PHYSICAL 0x00000000
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#define MSI_MIPS_ADDR_DM_LOGICAL 0x00000004
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/* Fields in data for Intel MSI messages. */
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#define MSI_MIPS_DATA_TRGRMOD 0x00008000 /* Trigger mode */
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#define MSI_MIPS_DATA_TRGREDG 0x00000000 /* edge */
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#define MSI_MIPS_DATA_TRGRLVL 0x00008000 /* level */
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#define MSI_MIPS_DATA_LEVEL 0x00004000 /* Polarity. */
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#define MSI_MIPS_DATA_DEASSERT 0x00000000
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#define MSI_MIPS_DATA_ASSERT 0x00004000
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#define MSI_MIPS_DATA_DELMOD 0x00000700 /* Delivery Mode */
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#define MSI_MIPS_DATA_DELFIXED 0x00000000 /* fixed */
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#define MSI_MIPS_DATA_DELLOPRI 0x00000100 /* lowest priority */
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#define MSI_MIPS_DATA_INTVEC 0x000000ff
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/*
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* Build Intel MSI message and data values from a source. AMD64 systems
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* seem to be compatible, so we use the same function for both.
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*/
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#define MIPS_MSI_ADDR(cpu) \
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(MSI_MIPS_ADDR_BASE | (cpu) << 12 | \
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MSI_MIPS_ADDR_RH_OFF | MSI_MIPS_ADDR_DM_PHYSICAL)
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#define MIPS_MSI_DATA(irq) \
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(MSI_MIPS_DATA_TRGRLVL | MSI_MIPS_DATA_DELFIXED | \
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MSI_MIPS_DATA_ASSERT | (irq))
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struct xlr_hose_softc {
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int junk; /* no softc */
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};
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static devclass_t pcib_devclass;
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static int pci_bus_status = 0;
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static void *pci_config_base;
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static uint32_t pci_cfg_read_32bit(uint32_t addr);
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static void pci_cfg_write_32bit(uint32_t addr, uint32_t data);
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static int
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xlr_pcib_probe(device_t dev)
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{
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device_set_desc(dev, "xlr system bridge controller");
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pci_init_resources();
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pci_config_base = (void *)MIPS_PHYS_TO_KSEG1(DEFAULT_PCI_CONFIG_BASE);
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pci_bus_status = 1;
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return 0;
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}
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static int
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xlr_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t * result)
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{
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#if 0
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device_printf(dev, "xlr_pcib_read_ivar : read ivar %d for child %s\n", which, device_get_nameunit(child));
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#endif
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switch (which) {
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case PCIB_IVAR_BUS:
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*result = 0;
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return 0;
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}
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return ENOENT;
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}
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static int
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xlr_pcib_maxslots(device_t dev)
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{
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if (xlr_board_info.is_xls)
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return 4;
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else
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return 32;
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}
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#define pci_cfg_offset(bus,slot,devfn,where) (((bus)<<16) + ((slot) << 11)+((devfn)<<8)+(where))
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static __inline__ void
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disable_and_clear_cache_error(void)
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{
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uint64_t lsu_cfg0 = read_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CFG0_REGID);
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lsu_cfg0 = lsu_cfg0 & ~0x2e;
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write_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CFG0_REGID, lsu_cfg0);
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/* Clear cache error log */
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write_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CERRLOG_REGID, 0);
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}
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static __inline__ void
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clear_and_enable_cache_error(void)
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{
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uint64_t lsu_cfg0 = 0;
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/* first clear the cache error logging register */
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write_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CERRLOG_REGID, 0);
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write_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CERROVF_REGID, 0);
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write_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CERRINT_REGID, 0);
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lsu_cfg0 = read_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CFG0_REGID);
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lsu_cfg0 = lsu_cfg0 | 0x2e;
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write_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CFG0_REGID, lsu_cfg0);
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}
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static uint32_t
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phoenix_pciread(u_int b, u_int s, u_int f,
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u_int reg, int width)
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{
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uint32_t data = 0;
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if ((width == 2) && (reg & 1))
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return 0xFFFFFFFF;
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else if ((width == 4) && (reg & 3))
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return 0xFFFFFFFF;
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if (pci_bus_status)
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data = pci_cfg_read_32bit(pci_cfg_offset(b, s, f, reg));
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else
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data = 0xFFFFFFFF;
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if (width == 1)
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return ((data >> ((reg & 3) << 3)) & 0xff);
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else if (width == 2)
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return ((data >> ((reg & 3) << 3)) & 0xffff);
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else
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return data;
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}
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static void
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phoenix_pciwrite(u_int b, u_int s, u_int f,
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u_int reg, u_int val, int width)
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{
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uint32_t cfgaddr = pci_cfg_offset(b, s, f, reg);
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uint32_t data = 0;
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if ((width == 2) && (reg & 1))
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return;
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else if ((width == 4) && (reg & 3))
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return;
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if (!pci_bus_status)
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return;
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if (width == 1) {
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data = pci_cfg_read_32bit(cfgaddr);
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data = (data & ~(0xff << ((reg & 3) << 3))) |
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(val << ((reg & 3) << 3));
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} else if (width == 2) {
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data = pci_cfg_read_32bit(cfgaddr);
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data = (data & ~(0xffff << ((reg & 3) << 3))) |
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(val << ((reg & 3) << 3));
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} else {
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data = val;
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}
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pci_cfg_write_32bit(cfgaddr, data);
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return;
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}
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static uint32_t
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pci_cfg_read_32bit(uint32_t addr)
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{
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uint32_t temp = 0;
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uint32_t *p = (uint32_t *) ((uint32_t) pci_config_base + (addr & ~3));
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uint64_t cerr_cpu_log = 0;
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disable_and_clear_cache_error();
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temp = SWAP32(*p);
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/* Read cache err log */
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cerr_cpu_log = read_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CERRLOG_REGID);
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if (cerr_cpu_log) {
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/* Device don't exist. */
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temp = ~0x0;
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}
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clear_and_enable_cache_error();
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return temp;
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}
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static void
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pci_cfg_write_32bit(uint32_t addr, uint32_t data)
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{
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unsigned int *p = (unsigned int *)((uint32_t) pci_config_base + (addr & ~3));
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*p = SWAP32(data);
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}
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static u_int32_t
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xlr_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
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u_int reg, int width)
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{
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return phoenix_pciread(b, s, f, reg, width);
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}
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static void
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xlr_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
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u_int reg, u_int32_t val, int width)
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{
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phoenix_pciwrite(b, s, f, reg, val, width);
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}
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static int
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xlr_pcib_attach(device_t dev)
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{
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device_add_child(dev, "pci", 0);
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bus_generic_attach(dev);
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return 0;
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}
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#define PCIE_LINK_STATE 0x4000
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static void
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xlr_pcib_identify(driver_t * driver, device_t parent)
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{
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xlr_reg_t *pcie_mmio_le = xlr_io_mmio(XLR_IO_PCIE_1_OFFSET);
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xlr_reg_t reg_link0 = xlr_read_reg(pcie_mmio_le, (0x80 >> 2));
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xlr_reg_t reg_link1 = xlr_read_reg(pcie_mmio_le, (0x84 >> 2));
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if ((uint16_t) reg_link0 & PCIE_LINK_STATE) {
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device_printf(parent, "Link 0 up\n");
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}
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if ((uint16_t) reg_link1 & PCIE_LINK_STATE) {
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device_printf(parent, "Link 1 up\n");
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}
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BUS_ADD_CHILD(parent, 0, "pcib", 0);
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}
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static int
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xlr_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs);
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static int
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xlr_release_msi(device_t pcib, device_t dev, int count, int *irqs);
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static int
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xlr_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
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{
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int pciirq;
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int i;
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device_t parent, tmp;
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/* find the lane on which the slot is connected to */
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tmp = dev;
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while (1) {
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parent = device_get_parent(tmp);
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if (parent == NULL || parent == pcib) {
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device_printf(dev, "Cannot find parent bus\n");
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return ENXIO;
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}
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if (strcmp(device_get_nameunit(parent), "pci0") == 0)
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break;
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tmp = parent;
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}
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switch (pci_get_slot(tmp)) {
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case 0:
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pciirq = PIC_PCIE_LINK0_IRQ;
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break;
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case 1:
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pciirq = PIC_PCIE_LINK1_IRQ;
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break;
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case 2:
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pciirq = PIC_PCIE_LINK2_IRQ;
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break;
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case 3:
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pciirq = PIC_PCIE_LINK3_IRQ;
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break;
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default:
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return ENXIO;
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}
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irqs[0] = pciirq;
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/*
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* For now put in some fixed values for the other requested MSI,
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* TODO handle multiple messages
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*/
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for (i = 1; i < count; i++)
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irqs[i] = pciirq + 64 * i;
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return 0;
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}
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static int
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xlr_release_msi(device_t pcib, device_t dev, int count, int *irqs)
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{
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device_printf(dev, "%s: msi release %d\n", device_get_nameunit(pcib), count);
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return 0;
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}
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static int
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xlr_map_msi(device_t pcib, device_t dev, int irq, uint64_t * addr, uint32_t * data);
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static int
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xlr_map_msi(device_t pcib, device_t dev, int irq, uint64_t * addr, uint32_t * data)
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{
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switch (irq) {
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case PIC_PCIE_LINK0_IRQ:
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case PIC_PCIE_LINK1_IRQ:
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case PIC_PCIE_LINK2_IRQ:
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case PIC_PCIE_LINK3_IRQ:
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*addr = MIPS_MSI_ADDR(0);
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*data = MIPS_MSI_DATA(irq);
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return 0;
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default:
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device_printf(dev, "%s: map_msi for irq %d - ignored", device_get_nameunit(pcib),
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irq);
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return (ENXIO);
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}
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}
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static device_method_t xlr_pcib_methods[] = {
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/* Device interface */
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DEVMETHOD(device_identify, xlr_pcib_identify),
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DEVMETHOD(device_probe, xlr_pcib_probe),
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DEVMETHOD(device_attach, xlr_pcib_attach),
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/* Bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_read_ivar, xlr_pcib_read_ivar),
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DEVMETHOD(bus_alloc_resource, xlr_pci_alloc_resource),
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DEVMETHOD(bus_release_resource, pci_release_resource),
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DEVMETHOD(bus_activate_resource, pci_activate_resource),
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DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
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DEVMETHOD(bus_setup_intr, mips_platform_pci_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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/* pcib interface */
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DEVMETHOD(pcib_maxslots, xlr_pcib_maxslots),
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DEVMETHOD(pcib_read_config, xlr_pcib_read_config),
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DEVMETHOD(pcib_write_config, xlr_pcib_write_config),
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DEVMETHOD(pcib_route_interrupt, mips_pci_route_interrupt),
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DEVMETHOD(pcib_alloc_msi, xlr_alloc_msi),
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DEVMETHOD(pcib_release_msi, xlr_release_msi),
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DEVMETHOD(pcib_map_msi, xlr_map_msi),
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{0, 0}
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};
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static driver_t xlr_pcib_driver = {
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"pcib",
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xlr_pcib_methods,
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sizeof(struct xlr_hose_softc),
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};
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DRIVER_MODULE(pcib, nexus, xlr_pcib_driver, pcib_devclass, 0, 0);
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