8cec0ab9a8
o fix race condition when processing rx descriptors: because we use a self-linked descriptor at the end of the rx descriptor list to avoid rx overruns (which can easily happen for 5212 parts that enable PHY errors) we must carefully check that a descriptor is "done" by looking ahead to the next descriptor before believing the done bit in the current descriptor (this is all handled in the HAL since the rx descriptor format is chip-specific so we need to pass in two additional parameters--the physical address of the current descriptor and the virtual address of the next descriptor in the list) o check copyout return status for SIOCGATHSTATS ioctl Approved by: re (scottl)
316 lines
13 KiB
C
316 lines
13 KiB
C
/*-
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* Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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* 3. Neither the names of the above-listed copyright holders nor the names
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* of any contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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/*
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* Defintions for the Atheros Wireless LAN controller driver.
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*/
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#ifndef _DEV_ATH_ATHVAR_H
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#define _DEV_ATH_ATHVAR_H
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#include <sys/taskqueue.h>
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#include <contrib/dev/ath/ah.h>
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#include <net80211/ieee80211_radiotap.h>
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#include <dev/ath/if_athioctl.h>
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#define ATH_TIMEOUT 1000
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#define ATH_RXBUF 40 /* number of RX buffers */
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#define ATH_TXBUF 60 /* number of TX buffers */
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#define ATH_TXDESC 8 /* number of descriptors per buffer */
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struct ath_recv_hist {
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int arh_ticks; /* sample time by system clock */
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u_int8_t arh_rssi; /* rssi */
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u_int8_t arh_antenna; /* antenna */
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};
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#define ATH_RHIST_SIZE 16 /* number of samples */
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#define ATH_RHIST_NOTIME (~0)
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/* driver-specific node */
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struct ath_node {
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struct ieee80211_node an_node; /* base class */
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u_int an_tx_ok; /* tx ok pkt */
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u_int an_tx_err; /* tx !ok pkt */
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u_int an_tx_retr; /* tx retry count */
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int an_tx_upper; /* tx upper rate req cnt */
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u_int an_tx_antenna; /* antenna for last good frame */
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u_int an_rx_antenna; /* antenna for last rcvd frame */
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struct ath_recv_hist an_rx_hist[ATH_RHIST_SIZE];
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u_int an_rx_hist_next;/* index of next ``free entry'' */
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};
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#define ATH_NODE(_n) ((struct ath_node *)(_n))
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struct ath_buf {
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TAILQ_ENTRY(ath_buf) bf_list;
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int bf_nseg;
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bus_dmamap_t bf_dmamap; /* DMA map of the buffer */
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struct ath_desc *bf_desc; /* virtual addr of desc */
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bus_addr_t bf_daddr; /* physical addr of desc */
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struct mbuf *bf_m; /* mbuf for buf */
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struct ieee80211_node *bf_node; /* pointer to the node */
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bus_size_t bf_mapsize;
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#define ATH_MAX_SCATTER 64
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bus_dma_segment_t bf_segs[ATH_MAX_SCATTER];
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};
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struct ath_softc {
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struct ieee80211com sc_ic; /* IEEE 802.11 common */
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int (*sc_newstate)(struct ieee80211com *,
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enum ieee80211_state, int);
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device_t sc_dev;
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bus_space_tag_t sc_st; /* bus space tag */
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bus_space_handle_t sc_sh; /* bus space handle */
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bus_dma_tag_t sc_dmat; /* bus DMA tag */
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struct mtx sc_mtx; /* master lock (recursive) */
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struct ath_hal *sc_ah; /* Atheros HAL */
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unsigned int sc_invalid : 1,/* disable hardware accesses */
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sc_doani : 1,/* dynamic noise immunity */
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sc_probing : 1;/* probing AP on beacon miss */
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/* rate tables */
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const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX];
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const HAL_RATE_TABLE *sc_currates; /* current rate table */
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enum ieee80211_phymode sc_curmode; /* current phy mode */
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u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */
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u_int8_t sc_hwmap[32]; /* h/w rate ix to IEEE table */
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HAL_INT sc_imask; /* interrupt mask copy */
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struct bpf_if *sc_drvbpf;
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union {
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struct ath_tx_radiotap_header th;
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u_int8_t pad[64];
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} u_tx_rt;
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union {
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struct ath_rx_radiotap_header th;
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u_int8_t pad[64];
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} u_rx_rt;
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struct ath_desc *sc_desc; /* TX/RX descriptors */
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bus_dma_segment_t sc_dseg;
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bus_dmamap_t sc_ddmamap; /* DMA map for descriptors */
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bus_addr_t sc_desc_paddr; /* physical addr of sc_desc */
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bus_addr_t sc_desc_len; /* size of sc_desc */
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struct task sc_fataltask; /* fatal int processing */
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struct task sc_rxorntask; /* rxorn int processing */
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TAILQ_HEAD(, ath_buf) sc_rxbuf; /* receive buffer */
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u_int32_t *sc_rxlink; /* link ptr in last RX desc */
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struct task sc_rxtask; /* rx int processing */
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u_int sc_txhalq; /* HAL q for outgoing frames */
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u_int32_t *sc_txlink; /* link ptr in last TX desc */
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int sc_tx_timer; /* transmit timeout */
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TAILQ_HEAD(, ath_buf) sc_txbuf; /* transmit buffer */
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struct mtx sc_txbuflock; /* txbuf lock */
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TAILQ_HEAD(, ath_buf) sc_txq; /* transmitting queue */
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struct mtx sc_txqlock; /* lock on txq and txlink */
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struct task sc_txtask; /* tx int processing */
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u_int sc_bhalq; /* HAL q for outgoing beacons */
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struct ath_buf *sc_bcbuf; /* beacon buffer */
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struct ath_buf *sc_bufptr; /* allocated buffer ptr */
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struct task sc_swbatask; /* swba int processing */
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struct task sc_bmisstask; /* bmiss int processing */
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struct callout sc_cal_ch; /* callout handle for cals */
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struct callout sc_scan_ch; /* callout handle for scan */
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struct ath_stats sc_stats; /* interface statistics */
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};
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#define sc_tx_th u_tx_rt.th
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#define sc_rx_th u_rx_rt.th
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#define ATH_LOCK_INIT(_sc) \
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mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
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MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE)
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#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
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#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
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#define ATH_TXBUF_LOCK_INIT(_sc) \
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mtx_init(&(_sc)->sc_txbuflock, \
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device_get_nameunit((_sc)->sc_dev), "xmit buf q", MTX_DEF)
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#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock)
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#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock)
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#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock)
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#define ATH_TXBUF_LOCK_ASSERT(_sc) \
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mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED)
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#define ATH_TXQ_LOCK_INIT(_sc) \
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mtx_init(&(_sc)->sc_txqlock, \
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device_get_nameunit((_sc)->sc_dev), "xmit q", MTX_DEF)
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#define ATH_TXQ_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txqlock)
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#define ATH_TXQ_LOCK(_sc) mtx_lock(&(_sc)->sc_txqlock)
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#define ATH_TXQ_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txqlock)
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#define ATH_TXQ_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_txqlock, MA_OWNED)
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int ath_attach(u_int16_t, struct ath_softc *);
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int ath_detach(struct ath_softc *);
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void ath_resume(struct ath_softc *);
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void ath_suspend(struct ath_softc *);
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void ath_shutdown(struct ath_softc *);
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void ath_intr(void *);
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/*
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* HAL definitions to comply with local coding convention.
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*/
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#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
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((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
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#define ath_hal_getratetable(_ah, _mode) \
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((*(_ah)->ah_getRateTable)((_ah), (_mode)))
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#define ath_hal_getregdomain(_ah) \
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((*(_ah)->ah_getRegDomain)((_ah)))
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#define ath_hal_getcountrycode(_ah) (_ah)->ah_countryCode
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#define ath_hal_getmac(_ah, _mac) \
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((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
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#define ath_hal_detach(_ah) \
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((*(_ah)->ah_detach)((_ah)))
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#define ath_hal_intrset(_ah, _mask) \
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((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
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#define ath_hal_intrget(_ah) \
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((*(_ah)->ah_getInterrupts)((_ah)))
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#define ath_hal_intrpend(_ah) \
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((*(_ah)->ah_isInterruptPending)((_ah)))
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#define ath_hal_getisr(_ah, _pmask) \
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((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
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#define ath_hal_updatetxtriglevel(_ah, _inc) \
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((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
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#define ath_hal_setpower(_ah, _mode, _sleepduration) \
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((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration)))
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#define ath_hal_keyreset(_ah, _ix) \
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((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
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#define ath_hal_keyset(_ah, _ix, _pk) \
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((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), NULL, AH_FALSE))
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#define ath_hal_keyisvalid(_ah, _ix) \
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(((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
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#define ath_hal_keysetmac(_ah, _ix, _mac) \
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((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
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#define ath_hal_getrxfilter(_ah) \
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((*(_ah)->ah_getRxFilter)((_ah)))
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#define ath_hal_setrxfilter(_ah, _filter) \
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((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
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#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
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((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
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#define ath_hal_waitforbeacon(_ah, _bf) \
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((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
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#define ath_hal_putrxbuf(_ah, _bufaddr) \
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((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
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#define ath_hal_gettsf32(_ah) \
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((*(_ah)->ah_getTsf32)((_ah)))
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#define ath_hal_gettsf64(_ah) \
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((*(_ah)->ah_getTsf64)((_ah)))
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#define ath_hal_resettsf(_ah) \
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((*(_ah)->ah_resetTsf)((_ah)))
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#define ath_hal_rxena(_ah) \
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((*(_ah)->ah_enableReceive)((_ah)))
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#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \
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((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
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#define ath_hal_gettxbuf(_ah, _q) \
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((*(_ah)->ah_getTxDP)((_ah), (_q)))
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#define ath_hal_getrxbuf(_ah) \
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((*(_ah)->ah_getRxDP)((_ah)))
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#define ath_hal_txstart(_ah, _q) \
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((*(_ah)->ah_startTxDma)((_ah), (_q)))
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#define ath_hal_setchannel(_ah, _chan) \
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((*(_ah)->ah_setChannel)((_ah), (_chan)))
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#define ath_hal_calibrate(_ah, _chan) \
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((*(_ah)->ah_perCalibration)((_ah), (_chan)))
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#define ath_hal_setledstate(_ah, _state) \
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((*(_ah)->ah_setLedState)((_ah), (_state)))
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#define ath_hal_beaconinit(_ah, _opmode, _nextb, _bperiod) \
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((*(_ah)->ah_beaconInit)((_ah), (_opmode), (_nextb), (_bperiod)))
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#define ath_hal_beaconreset(_ah) \
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((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
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#define ath_hal_beacontimers(_ah, _bs, _tsf, _dc, _cc) \
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((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs), (_tsf), \
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(_dc), (_cc)))
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#define ath_hal_setassocid(_ah, _bss, _associd) \
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((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd), 0))
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#define ath_hal_setopmode(_ah, _opmode) \
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((*(_ah)->ah_setPCUConfig)((_ah), (_opmode)))
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#define ath_hal_stoptxdma(_ah, _qnum) \
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((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
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#define ath_hal_stoppcurecv(_ah) \
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((*(_ah)->ah_stopPcuReceive)((_ah)))
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#define ath_hal_startpcurecv(_ah) \
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((*(_ah)->ah_startPcuReceive)((_ah)))
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#define ath_hal_stopdmarecv(_ah) \
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((*(_ah)->ah_stopDmaReceive)((_ah)))
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#define ath_hal_dumpstate(_ah) \
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((*(_ah)->ah_dumpState)((_ah)))
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#define ath_hal_getdiagstate(_ah, _id, _data, _size) \
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((*(_ah)->ah_getDiagState)((_ah), (_id), (_data), (_size)))
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#define ath_hal_setuptxqueue(_ah, _type, _irq) \
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((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
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#define ath_hal_resettxqueue(_ah, _q) \
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((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
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#define ath_hal_releasetxqueue(_ah, _q) \
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((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
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#define ath_hal_hasveol(_ah) \
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((*(_ah)->ah_hasVEOL)((_ah)))
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#define ath_hal_getrfgain(_ah) \
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((*(_ah)->ah_getRfGain)((_ah)))
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#define ath_hal_rxmonitor(_ah) \
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((*(_ah)->ah_rxMonitor)((_ah)))
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#define ath_hal_setupbeacondesc(_ah, _ds, _opmode, _flen, _hlen, \
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_rate, _antmode) \
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((*(_ah)->ah_setupBeaconDesc)((_ah), (_ds), (_opmode), \
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(_flen), (_hlen), (_rate), (_antmode)))
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#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
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((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
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#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \
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((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext)))
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#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
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_txr0, _txtr0, _keyix, _ant, _flags, \
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_rtsrate, _rtsdura) \
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((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
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(_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
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(_flags), (_rtsrate), (_rtsdura)))
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#define ath_hal_setupxtxdesc(_ah, _ds, _short, \
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_txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
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((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), (_short), \
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(_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
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#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last) \
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((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last)))
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#define ath_hal_txprocdesc(_ah, _ds) \
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((*(_ah)->ah_procTxDesc)((_ah), (_ds)))
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#endif /* _DEV_ATH_ATHVAR_H */
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