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receiving incoming traffics, try harder to gracefully stop active DMA cycles and then stop MACs. This is the way what datasheet recommends and seems to work reliably. Resetting controller while active DMAs are in progress is bad thing as we can't predict how DMAs touche allocated TX/RX buffers. This change ensures controller stop state before attempting to release allocated TX/RX buffers. Also update MAC statistics which could have been updated during the wait time of MAC stop. While I'm here remove unnecessary controller resets in various location. ste(4) no longer relies on hard controller reset to stop controller and resetting controller also clears all configured settings which makes it hard to implement WOL in near future. Now resetting a controller is performed in ste_init_locked().
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