e83ce34035
This adds support for the NVRAM handling and the basic SPROM hardware used on siba(4) and bcma(4) devices, including: * SPROM directly attached to the PCI core, accessible via PCI configuration space. * SPROM attached to later ChipCommon cores. * SPROM variables vended from the parent SoC bus (e.g. via a directly-attached flash device). Additional improvements to the NVRAM/SPROM interface will be required, but this changeset stands alone as working checkpoint. Submitted by: Landon Fuller <landonf@landonf.org> Reviewed by: Michael Zhilin <mizkha@gmail.com> (Broadcom MIPS support) Differential Revision: https://reviews.freebsd.org/D6196
136 lines
4.4 KiB
C
136 lines
4.4 KiB
C
/*-
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* Copyright (c) 2015 Landon Fuller <landon@landonf.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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#ifndef _BHND_CORES_CHIPC_CHIPCVAR_H_
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#define _BHND_CORES_CHIPC_CHIPCVAR_H_
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#include <dev/bhnd/nvram/bhnd_spromvar.h>
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#include "chipc.h"
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DECLARE_CLASS(bhnd_chipc);
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extern devclass_t bhnd_chipc_devclass;
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#define CHIPC_MAX_RES 1
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#define CHIPC_MAX_RSPEC (CHIPC_MAX_RES+1)
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/*
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* ChipCommon device quirks / features
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*/
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enum {
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/** No quirks */
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CHIPC_QUIRK_NONE = 0,
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/**
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* ChipCommon-controlled SPROM/OTP is supported, along with the
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* CHIPC_CAP_SPROM capability flag.
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*/
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CHIPC_QUIRK_SUPPORTS_SPROM = (1<<1),
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/**
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* External NAND NVRAM is supported, along with the CHIPC_CAP_NFLASH
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* capability flag.
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*/
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CHIPC_QUIRK_SUPPORTS_NFLASH = (1<<2),
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/**
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* The SPROM is attached via muxed pins. The pins must be switched
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* to allow reading/writing.
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*/
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CHIPC_QUIRK_MUX_SPROM = (1<<3),
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/**
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* Access to the SPROM uses pins shared with the 802.11a external PA.
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*
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* On modules using these 4331 packages, the CCTRL4331_EXTPA_EN flag
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* must be cleared to allow SPROM access.
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*/
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CHIPC_QUIRK_4331_EXTPA_MUX_SPROM = (1<<4) |
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CHIPC_QUIRK_MUX_SPROM,
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/**
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* Access to the SPROM uses pins shared with the 802.11a external PA.
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*
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* On modules using these 4331 chip packages, the external PA is
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* attached via GPIO 2, 5, and sprom_dout pins.
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*
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* When enabling and disabling EXTPA to allow SPROM access, the
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* CCTRL4331_EXTPA_ON_GPIO2_5 flag must also be set or cleared,
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* respectively.
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*/
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CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM = (1<<5) |
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CHIPC_QUIRK_4331_EXTPA_MUX_SPROM,
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/**
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* Access to the SPROM uses pins shared with two 802.11a external PAs.
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*
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* When enabling and disabling EXTPA, the CCTRL4331_EXTPA_EN2 must also
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* be cleared to allow SPROM access.
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*/
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CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM = (1<<6) |
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CHIPC_QUIRK_4331_EXTPA_MUX_SPROM,
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/**
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* SPROM pins are muxed with the FEM control lines on this 4360-family
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* device. The muxed pins must be switched to allow reading/writing
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* the SPROM.
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*/
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CHIPC_QUIRK_4360_FEM_MUX_SPROM = (1<<5) | CHIPC_QUIRK_MUX_SPROM
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};
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struct chipc_softc {
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device_t dev;
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struct resource_spec rspec[CHIPC_MAX_RSPEC];
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struct bhnd_resource *res[CHIPC_MAX_RES];
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struct bhnd_resource *core; /**< core registers. */
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struct bhnd_chipid ccid; /**< chip identification */
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uint32_t quirks; /**< CHIPC_QUIRK_* quirk flags */
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uint32_t caps; /**< CHIPC_CAP_* capability register flags */
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uint32_t cst; /**< CHIPC_CST* status register flags */
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bhnd_nvram_src_t nvram_src; /**< NVRAM source */
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struct mtx mtx; /**< state mutex. */
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struct bhnd_sprom sprom; /**< OTP/SPROM shadow, if any */
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};
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#define CHIPC_LOCK_INIT(sc) \
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mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
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"BHND chipc driver lock", MTX_DEF)
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#define CHIPC_LOCK(sc) mtx_lock(&(sc)->mtx)
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#define CHIPC_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
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#define CHIPC_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what)
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#define CHIPC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx)
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#endif /* _BHND_CORES_CHIPC_CHIPCVAR_H_ */ |