Jung-uk Kim 50d99d1a52 Enhanced floppy controllers have Data Rate Select Register (DSR) at 0x3f4. ... Use it to reset controller and to select data rate. According to Intel 80277AA datasheet, software reset behaves the same as DOR reset except that it is self clearing. National Semiconductor PC8477B datasheet says the same. As a side effect, we no longer use Configuration Control Register (CCR) at 0x3f7 for these controllers, which is often missing in modern hardware.		2006-07-06 21:12:18 +00:00
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cd180.h
cd1400.h
esp.h
hd64570.h
i8237.h
i8251.h
i8253reg.h	cosmetic change.	2005-05-14 10:26:31 +00:00
i8259.h	Typo.	2005-10-23 09:05:51 +00:00
i82586.h
nec765.h	Enhanced floppy controllers have Data Rate Select Register (DSR) at 0x3f4.	2006-07-06 21:12:18 +00:00
ns16550.h	Allow uart(4)'s ns8250 driver to work with devices whose regshift is > 0.	2006-05-23 00:41:12 +00:00
rsa.h
sab82532.h
via6522reg.h	Register definitions for the ancient via6522. This 20+ year-old chip	2005-12-02 22:36:14 +00:00
wd33c93reg.h
z8530.h	MFp4:	2006-02-24 02:03:35 +00:00