Oleksandr Tymoshenko 8f3b7d5616 Add new quirks:
- Data timeout is broken
  - Data timeout uses SD clock
  - Capabilities register is unavailable

Add calculations for clock divisor for SDHCI 3.0
2012-10-29 17:21:58 +00:00
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2012-10-27 22:13:42 +00:00
2012-10-28 02:55:51 +00:00
2012-10-10 08:36:38 +00:00
2012-10-29 17:21:58 +00:00
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2012-09-14 22:00:03 +00:00
2012-10-10 08:36:38 +00:00
2012-10-10 08:36:38 +00:00