e47b20bee2
- fix KV macro in t2_pci.c to include the sable_lynx_base variable so that the T2 CSRs can be found on lynxes. Current should be bootable on lynxes now.
209 lines
5.7 KiB
C
209 lines
5.7 KiB
C
/*-
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* Copyright (c) 2000 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPELCAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <pci/pcivar.h>
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#include <machine/swiz.h>
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#include <machine/md_var.h>
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#include <alpha/pci/t2reg.h>
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#include <alpha/pci/t2var.h>
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#include <alpha/pci/pcibus.h>
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#include "alphapci_if.h"
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#include "pcib_if.h"
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#define KV(pa) ALPHA_PHYS_TO_K0SEG((pa) + sable_lynx_base)
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static devclass_t pcib_devclass;
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static int
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t2_pcib_probe(device_t dev)
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{
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device_t child;
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device_set_desc(dev, "T2 PCI host bus adapter");
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pci_init_resources();
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child = device_add_child(dev, "pci", 0);
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device_set_ivars(child, 0);
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return 0;
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}
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static int
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t2_pcib_read_ivar(device_t dev, device_t child, int which, u_long *result)
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{
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if (which == PCIB_IVAR_BUS) {
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*result = 0;
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return 0;
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}
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return ENOENT;
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}
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static void *
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t2_pcib_cvt_dense(device_t dev, vm_offset_t addr)
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{
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addr &= 0xffffffffUL;
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return (void *) KV(addr | T2_PCI_DENSE);
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}
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static int
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t2_pcib_maxslots(device_t dev)
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{
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return 9;
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}
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#define T2_CFGOFF(b, s, f, r) \
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((b) ? (((b) << 16) | ((s) << 11) | ((f) << 8) | (r)) \
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: ((1 << ((s) + 11)) | ((f) << 8) | (r)))
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#define T2_TYPE1_SETUP(b,s,old_hae3) if((b)) { \
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do { \
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(s) = critical_enter(); \
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(old_hae3) = REGVAL(T2_HAE0_3); \
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alpha_mb(); \
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REGVAL(T2_HAE0_3) = (old_hae3) | (1<<30); \
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alpha_mb(); \
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} while(0); \
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}
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#define T2_TYPE1_TEARDOWN(b,s,old_hae3) if((b)) { \
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do { \
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alpha_mb(); \
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REGVAL(T2_HAE0_3) = (old_hae3); \
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alpha_mb(); \
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critical_exit((s)); \
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} while(0); \
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}
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#define SWIZ_CFGREAD(b, s, f, r, width, type) do { \
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type val = ~0; \
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int ipl = 0; \
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u_int32_t old_hae3 = 0; \
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vm_offset_t off = T2_CFGOFF(b, s, f, r); \
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vm_offset_t kv = SPARSE_##width##_ADDRESS(KV(T2_PCI_CONF), off); \
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alpha_mb(); \
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T2_TYPE1_SETUP(b,ipl,old_hae3); \
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if (!badaddr((caddr_t)kv, sizeof(type))) { \
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val = SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv)); \
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} \
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T2_TYPE1_TEARDOWN(b,ipl,old_hae3); \
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return val; \
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} while (0)
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#define SWIZ_CFGWRITE(b, s, f, r, data, width, type) do { \
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int ipl = 0; \
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u_int32_t old_hae3 = 0; \
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vm_offset_t off = T2_CFGOFF(b, s, f, r); \
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vm_offset_t kv = SPARSE_##width##_ADDRESS(KV(T2_PCI_CONF), off); \
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alpha_mb(); \
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T2_TYPE1_SETUP(b,ipl,old_hae3); \
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if (!badaddr((caddr_t)kv, sizeof(type))) { \
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SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data)); \
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alpha_wmb(); \
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} \
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T2_TYPE1_TEARDOWN(b,ipl,old_hae3); \
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return; \
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} while (0)
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static u_int32_t
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t2_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
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u_int reg, int width)
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{
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switch (width) {
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case 1:
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SWIZ_CFGREAD(b, s, f, reg, BYTE, u_int8_t);
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break;
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case 2:
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SWIZ_CFGREAD(b, s, f, reg, WORD, u_int16_t);
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break;
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case 4:
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SWIZ_CFGREAD(b, s, f, reg, LONG, u_int32_t);
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}
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return ~0;
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}
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static void
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t2_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
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u_int reg, u_int32_t val, int width)
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{
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switch (width) {
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case 1:
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SWIZ_CFGWRITE(b, s, f, reg, val, BYTE, u_int8_t);
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break;
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case 2:
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SWIZ_CFGWRITE(b, s, f, reg, val, WORD, u_int16_t);
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break;
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case 4:
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SWIZ_CFGWRITE(b, s, f, reg, val, LONG, u_int32_t);
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}
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}
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static device_method_t t2_pcib_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, t2_pcib_probe),
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DEVMETHOD(device_attach, bus_generic_attach),
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/* Bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_read_ivar, t2_pcib_read_ivar),
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DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
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DEVMETHOD(bus_release_resource, pci_release_resource),
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DEVMETHOD(bus_activate_resource, pci_activate_resource),
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DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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/* alphapci interface */
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DEVMETHOD(alphapci_cvt_dense, t2_pcib_cvt_dense),
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/* pcib interface */
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DEVMETHOD(pcib_maxslots, t2_pcib_maxslots),
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DEVMETHOD(pcib_read_config, t2_pcib_read_config),
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DEVMETHOD(pcib_write_config, t2_pcib_write_config),
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DEVMETHOD(pcib_route_interrupt, alpha_pci_route_interrupt),
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{ 0, 0 }
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};
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static driver_t t2_pcib_driver = {
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"pcib",
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t2_pcib_methods,
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1,
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};
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DRIVER_MODULE(pcib, t2, t2_pcib_driver, pcib_devclass, 0, 0);
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