718cf2ccb9
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
410 lines
15 KiB
C
410 lines
15 KiB
C
/*-
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* SPDX-License-Identifier: BSD-4-Clause
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*
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* Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Gardner Buchanan.
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* 4. The name of Gardner Buchanan may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* This file contains register information and access macros for
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* the SMC91xxx chipset.
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*
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* Information contained in this file was obtained from the SMC91C92
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* and SMC91C94 manuals from SMC. You will need one of these in order
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* to make any meaningful changes to this driver. Information about
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* obtaining one can be found at http://www.smc.com in the components
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* division.
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*
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* This FreeBSD driver is derived in part from the smc9194 Linux driver
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* by Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman.
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* It is also derived in part from the FreeBSD ep (3C509) driver which
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* is Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights
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* reserved.
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*
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*/
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#ifndef _IF_SNREG_H_
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#define _IF_SNREG_H_
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/*
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* Wait time for memory to be free. This probably shouldn't be
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* tuned that much, as waiting for this means nothing else happens
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* in the system
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*/
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#define MEMORY_WAIT_TIME 1000
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/* The SMC91xxx uses 16 I/O ports
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*/
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#define SMC_IO_EXTENT 16
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/*
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* A description of the SMC registers is probably in order here,
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* although for details, the SMC datasheet is invaluable.
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* The data sheet I (GB) am using is "SMC91C92 Single Chip Ethernet
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* Controller With RAM", Rev. 12/0/94. Constant definitions I give
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* here are loosely based on the mnemonic names given to them in the
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* data sheet, but there are many exceptions.
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*
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* Basically, the chip has 4 banks of registers (0 to 3), which
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* are accessed by writing a number into the BANK_SELECT register
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* (I also use a SMC_SELECT_BANK macro for this). Registers are
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* either Byte or Word sized. My constant definitions end in _B
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* or _W as appropriate.
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*
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* The banks are arranged so that for most purposes, bank 2 is all
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* that is needed for normal run time tasks.
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*/
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/*
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* Bank Select Register. This also doubles as
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* a chip identification register. This register
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* is mapped at the same position in all banks.
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*/
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#define BANK_SELECT_REG_W 0x0e
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#define BSR_DETECT_MASK 0xff00
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#define BSR_DETECT_VALUE 0x3300
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/* BANK 0
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*/
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/* Transmit Control Register controls some aspects of the transmit
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* behavior of the Ethernet Protocol Handler.
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*/
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#define TXMIT_CONTROL_REG_W 0x00
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#define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */
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#define TCR_LOOP 0x0002 /* Enable internal analogue loopback */
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#define TCR_FORCOL 0x0004 /* Force Collision on next TX */
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#define TCR_PAD_ENABLE 0x0080 /* Pad short packets to 64 bytes */
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#define TCR_NOCRC 0x0100 /* Do not append CRC */
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#define TCR_MON_CSN 0x0400 /* monitors the carrier status */
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#define TCR_FDUPLX 0x0800 /* receive packets sent out */
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#define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */
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#define TCR_EPH_LOOP 0x2000 /* Enable internal digital loopback */
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/* Status of the last transmitted frame and instantaneous status of
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* the Ethernet Protocol Handler jumbled together. In auto-release
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* mode this information is simply discarded after each TX. This info
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* is copied to the status word of in-memory packets after transmit
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* where relevant statuses can be checked.
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*/
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#define EPH_STATUS_REG_W 0x02
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#define EPHSR_TX_SUC 0x0001 /* Transmit was successful */
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#define EPHSR_SNGLCOL 0x0002 /* Single collision occurred */
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#define EPHSR_MULCOL 0x0004 /* Multiple Collisions occurred */
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#define EPHSR_LTX_MULT 0x0008 /* Transmit was a multicast */
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#define EPHSR_16COL 0x0010 /* 16 Collisions occurred, TX disabled */
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#define EPHSR_SQET 0x0020 /* SQE Test failed, TX disabled */
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#define EPHSR_LTX_BRD 0x0040 /* Transmit was a broadcast */
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#define EPHSR_DEFR 0x0080 /* TX deferred due to carrier det. */
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#define EPHSR_LATCOL 0x0200 /* Late collision detected, TX disabled */
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#define EPHSR_LOST_CAR 0x0400 /* Lost carrier sense, TX disabled */
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#define EPHSR_EXC_DEF 0x0800 /* Excessive deferrals in TX >2 MAXETHER
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* times */
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#define EPHSR_CTR_ROL 0x1000 /* Some ECR Counter(s) rolled over */
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#define EPHSR_RX_OVRN 0x2000 /* Receiver overrun, packets dropped */
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#define EPHSR_LINK_OK 0x4000 /* Link integrity is OK */
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#define EPHSR_TXUNRN 0x8000 /* Transmit underrun */
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/* Receiver Control Register controls some aspects of the receive
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* behavior of the Ethernet Protocol Handler.
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*/
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#define RECV_CONTROL_REG_W 0x04
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#define RCR_RX_ABORT 0x0001 /* Received huge packet */
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#define RCR_PROMISC 0x0002 /* enable promiscuous mode */
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#define RCR_ALMUL 0x0004 /* receive all multicast packets */
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#define RCR_ENABLE 0x0100 /* IFF this is set, we can receive packets */
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#define RCR_STRIP_CRC 0x0200 /* strips CRC */
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#define RCR_GAIN_BITS 0x0c00 /* PLL Gain control (for testing) */
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#define RCR_FILT_CAR 0x4000 /* Enable 12 bit carrier filter */
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#define RCR_SOFTRESET 0x8000 /* Resets the EPH logic */
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/* TX Statistics counters
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*/
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#define COUNTER_REG_W 0x06
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#define ECR_COLN_MASK 0x000f /* Vanilla collisions */
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#define ECR_MCOLN_MASK 0x00f0 /* Multiple collisions */
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#define ECR_DTX_MASK 0x0f00 /* Deferred transmits */
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#define ECR_EXDTX_MASK 0xf000 /* Excessively deferred transmits */
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/* Memory Information
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*/
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#define MEM_INFO_REG_W 0x08
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#define MIR_FREE_MASK 0xff00 /* Free memory pages available */
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#define MIR_TOTAL_MASK 0x00ff /* Total memory pages available */
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/* Memory Configuration
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*/
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#define MEM_CFG_REG_W 0x0a
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#define MCR_TXRSV_MASK 0x001f /* Count of pages reserved for transmit */
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/* Bank 0, Register 0x0c is unised in the SMC91C92
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*/
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/* BANK 1
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*/
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/* Adapter configuration
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*/
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#define CONFIG_REG_W 0x00
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#define CR_INT_SEL0 0x0002 /* Interrupt selector */
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#define CR_INT_SEL1 0x0004 /* Interrupt selector */
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#define CR_DIS_LINK 0x0040 /* Disable 10BaseT Link Test */
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#define CR_16BIT 0x0080 /* Bus width */
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#define CR_AUI_SELECT 0x0100 /* Use external (AUI) Transceiver */
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#define CR_SET_SQLCH 0x0200 /* Squelch level */
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#define CR_FULL_STEP 0x0400 /* AUI signalling mode */
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#define CR_NOW_WAIT_ST 0x1000 /* Disable bus wait states */
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/* The contents of this port are used by the adapter
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* to decode its I/O address. We use it as a varification
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* that the adapter is detected properly when probing.
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*/
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#define BASE_ADDR_REG_W 0x02 /* The select IO Base addr. */
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/* These registers hold the Ethernet MAC address.
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*/
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#define IAR_ADDR0_REG_W 0x04 /* My Ethernet address */
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#define IAR_ADDR1_REG_W 0x06 /* My Ethernet address */
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#define IAR_ADDR2_REG_W 0x08 /* My Ethernet address */
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/* General purpose register used for talking to the EEPROM.
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*/
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#define GENERAL_REG_W 0x0a
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/* Control register used for talking to the EEPROM and
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* setting some EPH functions.
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*/
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#define CONTROL_REG_W 0x0c
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#define CTR_STORE 0x0001 /* Store something to EEPROM */
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#define CTR_RELOAD 0x0002 /* Read EEPROM into registers */
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#define CTR_EEPROM_SEL 0x0004 /* Select registers for Reload/Store */
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#define CTR_TE_ENABLE 0x0020 /* Enable TX Error detection via EPH_INT */
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#define CTR_CR_ENABLE 0x0040 /* Enable Counter Rollover via EPH_INT */
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#define CTR_LE_ENABLE 0x0080 /* Enable Link Error detection via EPH_INT */
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#define CTR_AUTO_RELEASE 0x0800 /* Enable auto release mode for TX */
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#define CTR_POWERDOWN 0x2000 /* Enter powerdown mode */
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#define CTR_RCV_BAD 0x4000 /* Enable receipt of frames with bad CRC */
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/* BANK 2
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*/
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/* Memory Management Unit Control Register
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* Controls allocation of memory to receive and
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* transmit functions.
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*/
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#define MMU_CMD_REG_W 0x00
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#define MMUCR_BUSY 0x0001 /* MMU busy performing a release */
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/* MMU Commands:
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*/
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#define MMUCR_NOP 0x0000 /* Do nothing */
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#define MMUCR_ALLOC 0x0020 /* Or with number of 256 byte packets - 1 */
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#define MMUCR_RESET 0x0040 /* Reset MMU State */
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#define MMUCR_REMOVE 0x0060 /* Dequeue (but not free) current RX packet */
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#define MMUCR_RELEASE 0x0080 /* Dequeue and free the current RX packet */
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#define MMUCR_FREEPKT 0x00a0 /* Release packet in PNR register */
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#define MMUCR_ENQUEUE 0x00c0 /* Enqueue the packet for transmit */
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#define MMUCR_RESETTX 0x00e0 /* Reset transmit queues */
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/* Packet Number at TX Area
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*/
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#define PACKET_NUM_REG_B 0x02
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/* Packet number resulting from MMUCR_ALLOC
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*/
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#define ALLOC_RESULT_REG_B 0x03
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#define ARR_FAILED 0x80
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/* Transmit and receive queue heads
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*/
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#define FIFO_PORTS_REG_W 0x04
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#define FIFO_REMPTY 0x8000
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#define FIFO_TEMPTY 0x0080
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#define FIFO_RX_MASK 0x7f00
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#define FIFO_TX_MASK 0x007f
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/* The address within the packet for reading/writing. The
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* PTR_RCV bit is tricky. When PTR_RCV==1, the packet number
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* to be read is found in the FIFO_PORTS_REG_W, FIFO_RX_MASK.
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* When PTR_RCV==0, the packet number to be written is found
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* in the PACKET_NUM_REG_B.
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*/
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#define POINTER_REG_W 0x06
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#define PTR_READ 0x2000 /* Intended access mode */
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#define PTR_AUTOINC 0x4000 /* Do auto inc after read/write */
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#define PTR_RCV 0x8000 /* FIFO_RX is packet, otherwise PNR is packet */
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/* Data I/O register to be used in conjunction with
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* The pointer register to read and write data from the
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* card. The same register can be used for byte and word
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* ops.
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*/
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#define DATA_REG_W 0x08
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#define DATA_REG_B 0x08
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#define DATA_1_REG_B 0x08
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#define DATA_2_REG_B 0x0a
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/* Sense interrupt status (READ)
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*/
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#define INTR_STAT_REG_B 0x0c
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/* Acknowledge interrupt sources (WRITE)
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*/
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#define INTR_ACK_REG_B 0x0c
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/* Interrupt mask. Bit set indicates interrupt allowed.
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*/
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#define INTR_MASK_REG_B 0x0d
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/* Interrupts
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*/
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#define IM_RCV_INT 0x01 /* A packet has been received */
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#define IM_TX_INT 0x02 /* Packet TX complete */
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#define IM_TX_EMPTY_INT 0x04 /* No packets left to TX */
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#define IM_ALLOC_INT 0x08 /* Memory allocation completed */
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#define IM_RX_OVRN_INT 0x10 /* Receiver was overrun */
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#define IM_EPH_INT 0x20 /* Misc. EPH conditions (see CONTROL_REG_W) */
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#define IM_ERCV_INT 0x40 /* not on SMC9192 */
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/* BANK 3
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*/
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/* Multicast subscriptions.
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* The multicast handling in the SMC90Cxx is quite complicated. A table
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* of multicast address subscriptions is provided and a clever way of
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* speeding the search of that table by hashing is implemented in the
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* hardware. I have ignored this and simply subscribed to all multicasts
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* and let the kernel deal with the results.
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*/
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#define MULTICAST1_REG_W 0x00
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#define MULTICAST2_REG_W 0x02
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#define MULTICAST3_REG_W 0x04
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#define MULTICAST4_REG_W 0x06
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/* These registers do not exist on SMC9192, or at least
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* are not documented in the SMC91C92 data sheet.
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* The REVISION_REG_W register does however seem to work.
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*/
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#define MGMT_REG_W 0x08
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#define REVISION_REG_W 0x0a /* (hi: chip id low: rev #) */
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#define ERCV_REG_W 0x0c
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/* These are constants expected to be found in the
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* chip id register.
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*/
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#define CHIP_9190 3
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#define CHIP_9194 4
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#define CHIP_9195 5
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#define CHIP_91100 7
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#define CHIP_91100FD 8
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/* When packets are stuffed into the card or sucked out of the card
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* they are set up more or less as follows:
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*
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* Addr msbyte lsbyte
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* 00 SSSSSSSS SSSSSSSS - STATUS-WORD 16 bit TX or RX status
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* 02 RRRRR - RESERVED (unused)
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* 02 CCC CCCCCCCC - BYTE COUNT (RX: always even, TX: bit 0 ignored)
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* 04 DDDDDDDD DDDDDDDD - DESTINATION ADDRESS
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* 06 DDDDDDDD DDDDDDDD (48 bit Ethernet MAC Address)
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* 08 DDDDDDDD DDDDDDDD
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* 0A SSSSSSSS SSSSSSSS - SOURCE ADDRESS
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* 0C SSSSSSSS SSSSSSSS (48 bit Ethernet MAC Address)
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* 0E SSSSSSSS SSSSSSSS
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* 10 PPPPPPPP PPPPPPPP
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* .. PPPPPPPP PPPPPPPP
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* C-2 CCCCCCCC - CONTROL BYTE
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* C-2 PPPPPPPP - Last data byte (If odd length)
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*
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* The STATUS_WORD is derived from the EPH_STATUS_REG_W register
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* during transmit and is composed of another set of bits described
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* below during receive.
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*/
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/* Receive status bits. These values are found in the status word
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* field of a received packet. For receive packets I use the RS_ODDFRAME
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* to detect whether a frame has an extra byte on it. The CTLB_ODD
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* bit of the control byte tells the same thing.
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*/
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#define RS_MULTICAST 0x0001 /* Packet is multicast */
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#define RS_HASH_MASK 0x007e /* Mask of multicast hash value */
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#define RS_TOOSHORT 0x0400 /* Frame was a runt, <64 bytes */
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#define RS_TOOLONG 0x0800 /* Frame was giant, >1518 */
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#define RS_ODDFRAME 0x1000 /* Frame is odd lengthed */
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#define RS_BADCRC 0x2000 /* Frame had CRC error */
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#define RS_ALGNERR 0x8000 /* Frame had alignment error */
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#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
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#define RLEN_MASK 0x07ff /* Significant length bits in RX length */
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/* The control byte has the following significant bits.
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* For transmit, the CTLB_ODD bit specifies whether an extra byte
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* is present in the frame. Bit 0 of the byte count field is
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* ignored. I just pad every frame to even length and forget about
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* it.
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*/
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#define CTLB_CRC 0x10 /* Add CRC for this packet (TX only) */
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#define CTLB_ODD 0x20 /* The packet length is ODD */
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/*
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* I define some macros to make it easier to do somewhat common
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* or slightly complicated, repeated tasks.
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*/
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/* Select a register bank, 0 to 3
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*/
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#define SMC_SELECT_BANK(sc, x) { CSR_WRITE_2(sc, BANK_SELECT_REG_W, (x)); }
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/* Define a small delay for the reset
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*/
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#define SMC_DELAY(sc) { CSR_READ_2(sc, RECV_CONTROL_REG_W); \
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CSR_READ_2(sc, RECV_CONTROL_REG_W); \
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CSR_READ_2(sc, RECV_CONTROL_REG_W); }
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#endif /* _IF_SNREG_H_ */
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