314 lines
7.6 KiB
C
314 lines
7.6 KiB
C
/*-
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* Copyright (c) 2017 Hiroki Mori. All rights reserved.
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* Copyright (c) 2017 Ian Lepore. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* This code base on isl12xx.c
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Driver for realtime clock HAOYU HYM8563
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*/
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/clock.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#ifdef FDT
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#endif
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#include <dev/iicbus/iiconf.h>
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#include <dev/iicbus/iicbus.h>
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#include "clock_if.h"
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#include "iicbus_if.h"
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/* Registers */
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#define HYM8563_CTRL1 0x00
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#define HYM8563_CTRL1_TEST (1 << 7)
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#define HYM8563_CTRL1_STOP (1 << 5)
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#define HYM8563_CTRL1_TESTC (1 << 3)
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#define HYM8563_CTRL2 0x01
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#define HYM8563_CTRL2_TI_TP (1 << 4)
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#define HYM8563_CTRL2_AF (1 << 3)
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#define HYM8563_CTRL2_TF (1 << 2)
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#define HYM8563_CTRL2_AIE (1 << 1)
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#define HYM8563_CTRL2_TIE (1 << 0)
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#define HYM8563_SEC 0x02 /* plus battery low bit */
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#define HYM8563_SEC_VL (1 << 7)
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#define HYM8563_MIN 0x03
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#define HYM8563_HOUR 0x04
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#define HYM8563_DAY 0x05
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#define HYM8563_WEEKDAY 0x06
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#define HYM8563_MONTH 0x07 /* plus 1 bit for century */
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#define HYM8563_MONTH_CENTURY (1 << 7)
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#define HYM8563_YEAR 0x08
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struct hym8563_softc {
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device_t dev;
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struct intr_config_hook init_hook;
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};
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#ifdef FDT
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static struct ofw_compat_data compat_data[] = {
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{"haoyu,hym8563", 1},
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{NULL, 0},
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};
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#endif
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static inline int
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hym8563_read_buf(struct hym8563_softc *sc, uint8_t reg, uint8_t *buf,
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uint16_t buflen)
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{
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return (iicdev_readfrom(sc->dev, reg, buf, buflen, IIC_WAIT));
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}
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static inline int
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hym8563_write_buf(struct hym8563_softc *sc, uint8_t reg, uint8_t *buf,
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uint16_t buflen)
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{
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return (iicdev_writeto(sc->dev, reg, buf, buflen, IIC_WAIT));
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}
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static inline int
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hym8563_read_1(struct hym8563_softc *sc, uint8_t reg, uint8_t *data)
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{
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return (iicdev_readfrom(sc->dev, reg, data, 1, IIC_WAIT));
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}
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static inline int
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hym8563_write_1(struct hym8563_softc *sc, uint8_t reg, uint8_t val)
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{
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return (iicdev_writeto(sc->dev, reg, &val, 1, IIC_WAIT));
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}
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static int
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hym8563_gettime(device_t dev, struct timespec *ts)
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{
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struct hym8563_softc *sc;
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struct bcd_clocktime bct;
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uint8_t buf[7];
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int rv;
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sc = device_get_softc(dev);
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/* Read all RTC data */
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rv = hym8563_read_buf(sc, HYM8563_SEC, buf, sizeof(buf));
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if (rv != 0) {
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device_printf(sc->dev, "Cannot read time registers: %d\n", rv);
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return (rv);
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}
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/* Check for low voltage flag */
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if (buf[0] & HYM8563_SEC_VL)
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{
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device_printf(sc->dev,
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"WARNING: RTC battery failed; time is invalid\n");
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return (EINVAL);
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}
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bzero(&bct, sizeof(bct));
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bct.sec = buf[0] & 0x7F;
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bct.min = buf[1] & 0x7F;
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bct.hour = buf[2] & 0x3f;
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bct.day = buf[3] & 0x3f;
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/* buf[4] is weekday */
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bct.mon = buf[5] & 0x1f;
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bct.year = buf[6] & 0xff;
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if (buf[5] & HYM8563_MONTH_CENTURY)
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bct.year += 0x100;
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clock_dbgprint_bcd(sc->dev, CLOCK_DBG_READ, &bct);
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return (clock_bcd_to_ts(&bct, ts, false));
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}
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static int
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hym8563_settime(device_t dev, struct timespec *ts)
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{
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struct hym8563_softc *sc;
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struct bcd_clocktime bct;
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uint8_t buf[7];
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int rv;
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sc = device_get_softc(dev);
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ts->tv_sec -= utc_offset();
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clock_ts_to_bcd(ts, &bct, false);
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clock_dbgprint_bcd(sc->dev, CLOCK_DBG_WRITE, &bct);
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buf[0] = bct.sec; /* Also clear VL flag */
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buf[1] = bct.min;
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buf[2] = bct.hour;
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buf[3] = bct.day;
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buf[4] = bct.dow;
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buf[5] = bct.mon;
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buf[6] = bct.year & 0xFF;
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if (bct.year > 0x99)
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buf[5] |= HYM8563_MONTH_CENTURY;
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/* Stop RTC */
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rv = hym8563_write_1(sc, HYM8563_CTRL1, HYM8563_CTRL1_STOP);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot write CTRL1 register: %d\n", rv);
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return (rv);
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}
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/* Write all RTC data */
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rv = hym8563_write_buf(sc, HYM8563_SEC, buf, sizeof(buf));
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if (rv != 0) {
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device_printf(sc->dev, "Cannot write time registers: %d\n", rv);
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return (rv);
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}
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return (rv);
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/* Start RTC again */
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rv = hym8563_write_1(sc, HYM8563_CTRL1, 0);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot write CTRL1 register: %d\n", rv);
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return (rv);
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}
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return (0);
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}
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static void
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hym8563_init(void *arg)
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{
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struct hym8563_softc *sc;
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uint8_t reg;
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int rv;
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sc = (struct hym8563_softc*)arg;
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config_intrhook_disestablish(&sc->init_hook);
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/* Clear CTL1 register (stop and test bits) */
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rv = hym8563_write_1(sc, HYM8563_CTRL1, 0);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot init CTRL1 register: %d\n", rv);
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return;
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}
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/* Disable interrupts and alarms */
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rv = hym8563_read_1(sc, HYM8563_CTRL2, ®);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot read CTRL2 register: %d\n", rv);
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return;
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}
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rv &= ~HYM8563_CTRL2_TI_TP;
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rv &= ~HYM8563_CTRL2_AF;
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rv &= ~HYM8563_CTRL2_TF;
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rv = hym8563_write_1(sc, HYM8563_CTRL2, 0);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot write CTRL2 register: %d\n", rv);
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return;
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}
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/*
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* Register as a system realtime clock.
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*/
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clock_register_flags(sc->dev, 1000000, 0);
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clock_schedule(sc->dev, 1);
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return;
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}
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static int
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hym8563_probe(device_t dev)
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{
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#ifdef FDT
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
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device_set_desc(dev, "HYM8694 RTC");
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return (BUS_PROBE_DEFAULT);
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}
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#endif
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return (ENXIO);
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}
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static int
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hym8563_attach(device_t dev)
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{
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struct hym8563_softc *sc;
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sc = device_get_softc(dev);
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sc->dev = dev;
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/*
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* Chip init must wait until interrupts are enabled. Often i2c access
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* works only when the interrupts are available.
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*/
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sc->init_hook.ich_func = hym8563_init;
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sc->init_hook.ich_arg = sc;
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if (config_intrhook_establish(&sc->init_hook) != 0)
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return (ENOMEM);
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return (0);
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}
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static int
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hym8563_detach(device_t dev)
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{
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clock_unregister(dev);
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return (0);
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}
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static device_method_t hym8563_methods[] = {
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/* device_if methods */
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DEVMETHOD(device_probe, hym8563_probe),
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DEVMETHOD(device_attach, hym8563_attach),
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DEVMETHOD(device_detach, hym8563_detach),
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/* clock_if methods */
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DEVMETHOD(clock_gettime, hym8563_gettime),
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DEVMETHOD(clock_settime, hym8563_settime),
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DEVMETHOD_END,
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};
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static devclass_t hym8563_devclass;
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static DEFINE_CLASS_0(hym8563_rtc, hym8563_driver, hym8563_methods,
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sizeof(struct hym8563_softc));
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DRIVER_MODULE(hym8563, iicbus, hym8563_driver, hym8563_devclass, NULL, NULL);
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MODULE_VERSION(hym8563, 1);
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MODULE_DEPEND(hym8563, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER);
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IICBUS_FDT_PNP_INFO(compat_data); |