e9e2a7c1d3
Linux device tree binding, whose usage is obligatory, comprises faulty representation of Marvell cryptographic engine (CESA) - two engines are artificially gathered into single DT node, in order to avoid certain SW limitation. This patch improves the cesa driver to support above binding, depending on compatible string, which helps to ensure backward compatibility. Submitted by: Patryk Duda Obtained from: Semihalf Sponsored by: Stormshield Differential Revision: https://reviews.freebsd.org/D14760
395 lines
13 KiB
C
395 lines
13 KiB
C
/*-
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD.
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* All rights reserved.
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*
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* Developed by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of MARVELL nor the names of contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MVWIN_H_
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#define _MVWIN_H_
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/*
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* Decode windows addresses.
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*
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* All decoding windows must be aligned to their size, which has to be
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* a power of 2.
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*/
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/*
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* SoC Integrated devices: 0xF1000000, 16 MB (VA == PA)
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*/
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/* SoC Regs */
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#define MV_PHYS_BASE 0xF1000000
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#define MV_SIZE (1024 * 1024) /* 1 MB */
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/* SRAM */
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#define MV_CESA_SRAM_BASE 0xF1100000
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/*
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* External devices: 0x80000000, 1 GB (VA == PA)
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* Includes Device Bus, PCI and PCIE.
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*/
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#if defined(SOC_MV_ORION)
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#define MV_PCI_PORTS 2 /* 1x PCI + 1x PCIE */
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#elif defined(SOC_MV_KIRKWOOD)
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#define MV_PCI_PORTS 1 /* 1x PCIE */
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#elif defined(SOC_MV_DISCOVERY)
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#define MV_PCI_PORTS 8 /* 8x PCIE */
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#else
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#define MV_PCI_PORTS 1 /* 1x PCIE -> worst case */
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#endif
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/* PCI/PCIE Memory */
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#define MV_PCI_MEM_PHYS_BASE 0x80000000
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#define MV_PCI_MEM_SIZE (512 * 1024 * 1024) /* 512 MB */
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#define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE
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#define MV_PCI_MEM_SLICE_SIZE (MV_PCI_MEM_SIZE / MV_PCI_PORTS)
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/* PCI/PCIE I/O */
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#define MV_PCI_IO_PHYS_BASE 0xBF000000
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#define MV_PCI_IO_SIZE (16 * 1024 * 1024) /* 16 MB */
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#define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE
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#define MV_PCI_IO_SLICE_SIZE (MV_PCI_IO_SIZE / MV_PCI_PORTS)
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#define MV_PCI_VA_MEM_BASE 0
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#define MV_PCI_VA_IO_BASE 0
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/*
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* Device Bus (VA == PA)
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*/
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#define MV_DEV_BOOT_BASE 0xF9300000
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#define MV_DEV_BOOT_SIZE (1024 * 1024) /* 1 MB */
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#define MV_DEV_CS0_BASE 0xF9400000
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#define MV_DEV_CS0_SIZE (1024 * 1024) /* 1 MB */
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#define MV_DEV_CS1_BASE 0xF9500000
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#define MV_DEV_CS1_SIZE (32 * 1024 * 1024) /* 32 MB */
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#define MV_DEV_CS2_BASE 0xFB500000
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#define MV_DEV_CS2_SIZE (1024 * 1024) /* 1 MB */
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/*
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* Integrated SoC peripherals addresses
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*/
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#define MV_BASE MV_PHYS_BASE /* VA == PA mapping */
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#define MV_DDR_CADR_BASE_ARMV7 (MV_BASE + 0x20180)
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#define MV_DDR_CADR_BASE (MV_BASE + 0x1500)
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#define MV_MPP_BASE (MV_BASE + 0x10000)
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#define MV_MISC_BASE (MV_BASE + 0x18200)
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#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000)
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#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80)
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#define MV_MP_CLOCKS_BASE (MV_MBUS_BRIDGE_BASE + 0x700)
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#define MV_CPU_CONTROL_BASE_ARMV7 (MV_MBUS_BRIDGE_BASE + 0x1800)
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#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100)
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#define MV_PCI_BASE (MV_BASE + 0x30000)
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#define MV_PCI_SIZE 0x2000
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#define MV_PCIE_BASE_ARMADA38X (MV_BASE + 0x80000)
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#define MV_PCIE_BASE (MV_BASE + 0x40000)
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#define MV_PCIE_SIZE 0x2000
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#define MV_SDIO_BASE (MV_BASE + 0x90000)
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#define MV_SDIO_SIZE 0x10000
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/*
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* Decode windows definitions and macros
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*/
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#define MV_WIN_CPU_CTRL_ARMV7(n) (((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8)))
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#define MV_WIN_CPU_BASE_ARMV7(n) ((((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) + 0x4)
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#define MV_WIN_CPU_REMAP_LO_ARMV7(n) (0x10 * (n) + 0x008)
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#define MV_WIN_CPU_REMAP_HI_ARMV7(n) (0x10 * (n) + 0x00C)
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#define MV_WIN_CPU_CTRL_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880))
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#define MV_WIN_CPU_BASE_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884))
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#define MV_WIN_CPU_REMAP_LO_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888))
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#define MV_WIN_CPU_REMAP_HI_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C))
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#if defined(SOC_MV_DISCOVERY)
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#define MV_WIN_CPU_MAX 14
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#else
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#define MV_WIN_CPU_MAX 8
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#endif
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#define MV_WIN_CPU_MAX_ARMV7 20
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#define MV_WIN_CPU_ATTR_SHIFT 8
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#define MV_WIN_CPU_TARGET_SHIFT 4
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#define MV_WIN_CPU_ENABLE_BIT 1
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#define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0)
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#define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4)
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#define MV_WIN_DDR_MAX 4
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/*
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* These values are valid only for peripherals decoding windows
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* Bit in ATTR is zeroed according to CS bank number
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*/
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#define MV_WIN_DDR_ATTR(cs) (0x0F & ~(0x01 << (cs)))
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#define MV_WIN_DDR_TARGET 0x0
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#if defined(SOC_MV_DISCOVERY)
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#define MV_WIN_CESA_TARGET 9
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#define MV_WIN_CESA_ATTR(eng_sel) 1
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#else
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#define MV_WIN_CESA_TARGET 3
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#define MV_WIN_CESA_ATTR(eng_sel) 0
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#endif
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#define MV_WIN_CESA_TARGET_ARMADAXP 9
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/*
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* Bits [2:3] of cesa attribute select engine:
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* eng_sel:
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* 1: engine1
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* 2: engine0
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*/
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#define MV_WIN_CESA_ATTR_ARMADAXP(eng_sel) (1 | ((eng_sel) << 2))
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#define MV_WIN_CESA_TARGET_ARMADA38X 9
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/*
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* Bits [1:0] = Data swapping
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* 0x0 = Byte swap
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* 0x1 = No swap
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* 0x2 = Byte and word swap
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* 0x3 = Word swap
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* Bits [4:2] = CESA select:
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* 0x6 = CESA0
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* 0x5 = CESA1
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*/
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#define MV_WIN_CESA_ATTR_ARMADA38X(eng_sel) (0x11 | (1 << (3 - (eng_sel))))
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/* CESA TDMA address decoding registers */
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#define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xA04)
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#define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xA00)
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#define MV_WIN_CESA_MAX 4
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#define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x320)
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#define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x324)
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#define MV_WIN_USB_MAX 4
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#define MV_WIN_USB3_CTRL(n) (0x8 * (n) + 0x4000)
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#define MV_WIN_USB3_BASE(n) (0x8 * (n) + 0x4004)
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#define MV_WIN_USB3_MAX 8
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#define MV_WIN_NETA_OFFSET 0x2000
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#define MV_WIN_NETA_BASE(n) MV_WIN_ETH_BASE(n) + MV_WIN_NETA_OFFSET
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#define MV_WIN_CESA_OFFSET 0x2000
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#define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200)
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#define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204)
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#define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280)
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#define MV_WIN_ETH_MAX 6
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#define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00)
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#define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04)
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#define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60)
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#define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70)
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#define MV_WIN_IDMA_MAX 8
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#define MV_IDMA_CHAN_MAX 4
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#define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100)
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#define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100)
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#define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100)
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#define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100)
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#define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100)
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#define MV_WIN_XOR_MAX 8
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#define MV_XOR_CHAN_MAX 2
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#define MV_XOR_NON_REMAP 4
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#define MV_WIN_PCIE_TARGET_ARMADAXP(n) (4 + (4 * ((n) % 2)))
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#define MV_WIN_PCIE_MEM_ATTR_ARMADAXP(n) (0xE8 + (0x10 * ((n) / 2)))
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#define MV_WIN_PCIE_IO_ATTR_ARMADAXP(n) (0xE0 + (0x10 * ((n) / 2)))
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#define MV_WIN_PCIE_TARGET_ARMADA38X(n) ((n) == 0 ? 8 : 4)
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#define MV_WIN_PCIE_MEM_ATTR_ARMADA38X(n) ((n) < 2 ? 0xE8 : (0xD8 - (((n) % 2) * 0x20)))
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#define MV_WIN_PCIE_IO_ATTR_ARMADA38X(n) ((n) < 2 ? 0xE0 : (0xD0 - (((n) % 2) * 0x20)))
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#if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_KIRKWOOD)
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#define MV_WIN_PCIE_TARGET(n) 4
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#define MV_WIN_PCIE_MEM_ATTR(n) 0xE8
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#define MV_WIN_PCIE_IO_ATTR(n) 0xE0
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#elif defined(SOC_MV_ORION)
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#define MV_WIN_PCIE_TARGET(n) 4
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#define MV_WIN_PCIE_MEM_ATTR(n) 0x59
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#define MV_WIN_PCIE_IO_ATTR(n) 0x51
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#else
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#define MV_WIN_PCIE_TARGET(n) (4 + (4 * ((n) % 2)))
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#define MV_WIN_PCIE_MEM_ATTR(n) (0xE8 + (0x10 * ((n) / 2)))
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#define MV_WIN_PCIE_IO_ATTR(n) (0xE0 + (0x10 * ((n) / 2)))
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#endif
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#define MV_WIN_PCI_TARGET 3
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#define MV_WIN_PCI_MEM_ATTR 0x59
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#define MV_WIN_PCI_IO_ATTR 0x51
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#define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \
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(n) + 1) + 0x1820)
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#define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \
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(n) + 1) + 0x1824)
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#define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \
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(n) + 1) + 0x182C)
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#define MV_WIN_PCIE_MAX 6
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#define MV_PCIE_BAR_CTRL(n) (0x04 * (n) + 0x1800)
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#define MV_PCIE_BAR_BASE(n) (0x08 * ((n) < 3 ? (n) : 4) + 0x0010)
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#define MV_PCIE_BAR_BASE_H(n) (0x08 * (n) + 0x0014)
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#define MV_PCIE_BAR_MAX 4
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#define MV_PCIE_BAR_64BIT (0x4)
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#define MV_PCIE_BAR_PREFETCH_EN (0x8)
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#define MV_PCIE_CONTROL (0x1a00)
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#define MV_PCIE_ROOT_CMPLX (1 << 1)
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#define MV_WIN_SATA_CTRL_ARMADA38X(n) (0x10 * (n) + 0x60)
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#define MV_WIN_SATA_BASE_ARMADA38X(n) (0x10 * (n) + 0x64)
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#define MV_WIN_SATA_SIZE_ARMADA38X(n) (0x10 * (n) + 0x68)
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#define MV_WIN_SATA_MAX_ARMADA38X 4
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#define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30)
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#define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34)
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#define MV_WIN_SATA_MAX 4
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#define MV_WIN_SDHCI_CTRL(n) (0x8 * (n) + 0x4080)
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#define MV_WIN_SDHCI_BASE(n) (0x8 * (n) + 0x4084)
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#define MV_WIN_SDHCI_MAX 8
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#define MV_BOOTROM_MEM_ADDR 0xFFF00000
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#define MV_BOOTROM_WIN_SIZE 0xF
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#define MV_CPU_SUBSYS_REGS_LEN 0x100
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#define IO_WIN_9_CTRL_OFFSET 0x98
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#define IO_WIN_9_BASE_OFFSET 0x9C
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/* Mbus decoding unit IDs and attributes */
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#define MBUS_BOOTROM_TGT_ID 0x1
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#define MBUS_BOOTROM_ATTR 0x1D
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/* Internal Units Sync Barrier Control Register */
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#define MV_SYNC_BARRIER_CTRL 0x84
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#define MV_SYNC_BARRIER_CTRL_ALL 0xFFFF
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/* IO Window Control Register fields */
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#define IO_WIN_SIZE_SHIFT 16
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#define IO_WIN_SIZE_MASK 0xFFFF
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#define IO_WIN_COH_ATTR_MASK (0xF << 12)
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#define IO_WIN_ATTR_SHIFT 8
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#define IO_WIN_ATTR_MASK 0xFF
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#define IO_WIN_TGT_SHIFT 4
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#define IO_WIN_TGT_MASK 0xF
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#define IO_WIN_SYNC_SHIFT 1
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#define IO_WIN_SYNC_MASK 0x1
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#define IO_WIN_ENA_SHIFT 0
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#define IO_WIN_ENA_MASK 0x1
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#define WIN_REG_IDX_RD(pre,reg,off,base) \
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static __inline uint32_t \
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pre ## _ ## reg ## _read(int i) \
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{ \
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return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \
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}
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#define WIN_REG_IDX_RD2(pre,reg,off,base) \
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static __inline uint32_t \
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pre ## _ ## reg ## _read(int i, int j) \
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{ \
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return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \
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} \
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#define WIN_REG_BASE_IDX_RD(pre,reg,off) \
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static __inline uint32_t \
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pre ## _ ## reg ## _read(uint32_t base, int i) \
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{ \
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return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \
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}
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#define WIN_REG_BASE_IDX_RD2(pre,reg,off) \
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static __inline uint32_t \
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pre ## _ ## reg ## _read(uint32_t base, int i, int j) \
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{ \
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return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \
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}
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#define WIN_REG_IDX_WR(pre,reg,off,base) \
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static __inline void \
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pre ## _ ## reg ## _write(int i, uint32_t val) \
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{ \
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bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \
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}
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#define WIN_REG_IDX_WR2(pre,reg,off,base) \
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static __inline void \
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pre ## _ ## reg ## _write(int i, int j, uint32_t val) \
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{ \
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bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \
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}
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#define WIN_REG_BASE_IDX_WR(pre,reg,off) \
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static __inline void \
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pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \
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{ \
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bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \
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}
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#define WIN_REG_BASE_IDX_WR2(pre,reg,off) \
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static __inline void \
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pre ## _ ## reg ## _write(uint32_t base, int i, int j, uint32_t val) \
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{ \
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bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \
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}
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#define WIN_REG_RD(pre,reg,off,base) \
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static __inline uint32_t \
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pre ## _ ## reg ## _read(void) \
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{ \
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return (bus_space_read_4(fdtbus_bs_tag, base, off)); \
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}
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#define WIN_REG_BASE_RD(pre,reg,off) \
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static __inline uint32_t \
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pre ## _ ## reg ## _read(uint32_t base) \
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{ \
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return (bus_space_read_4(fdtbus_bs_tag, base, off)); \
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}
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#define WIN_REG_WR(pre,reg,off,base) \
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static __inline void \
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pre ## _ ## reg ## _write(uint32_t val) \
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{ \
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bus_space_write_4(fdtbus_bs_tag, base, off, val); \
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}
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#define WIN_REG_BASE_WR(pre,reg,off) \
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static __inline void \
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pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \
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{ \
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bus_space_write_4(fdtbus_bs_tag, base, off, val); \
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}
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#endif /* _MVWIN_H_ */
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