b41169fdce
We failed to setup PCI devices on slot 31 and that's where the SATA controller is for the P2020 eval board.
851 lines
22 KiB
C
851 lines
22 KiB
C
/*-
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* Copyright 2006-2007 by Juniper Networks.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/ktr.h>
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#include <sys/sockio.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <sys/queue.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/endian.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include "pcib_if.h"
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <machine/intr_machdep.h>
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#include <machine/ocpbus.h>
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#include <machine/spr.h>
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#include <powerpc/mpc85xx/ocpbus.h>
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#define REG_CFG_ADDR 0x0000
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#define CONFIG_ACCESS_ENABLE 0x80000000
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#define REG_CFG_DATA 0x0004
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#define REG_INT_ACK 0x0008
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#define REG_POTAR(n) (0x0c00 + 0x20 * (n))
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#define REG_POTEAR(n) (0x0c04 + 0x20 * (n))
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#define REG_POWBAR(n) (0x0c08 + 0x20 * (n))
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#define REG_POWAR(n) (0x0c10 + 0x20 * (n))
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#define REG_PITAR(n) (0x0e00 - 0x20 * (n))
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#define REG_PIWBAR(n) (0x0e08 - 0x20 * (n))
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#define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n))
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#define REG_PIWAR(n) (0x0e10 - 0x20 * (n))
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#define PCIR_FSL_LTSSM 0x404
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#define FSL_LTSSM_L0 0x16
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#define DEVFN(b, s, f) ((b << 16) | (s << 8) | f)
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struct pci_ocp_softc {
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device_t sc_dev;
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struct rman sc_iomem;
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bus_addr_t sc_iomem_va; /* Virtual mapping. */
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bus_addr_t sc_iomem_alloc; /* Next allocation. */
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struct rman sc_ioport;
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bus_addr_t sc_ioport_va; /* Virtual mapping. */
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bus_addr_t sc_ioport_alloc; /* Next allocation. */
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struct resource *sc_res;
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bus_space_handle_t sc_bsh;
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bus_space_tag_t sc_bst;
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int sc_rid;
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int sc_busnr;
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uint8_t sc_pcie_cap;
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/* Devices that need special attention. */
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int sc_devfn_tundra;
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int sc_devfn_via_ide;
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};
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static int pci_ocp_attach(device_t);
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static int pci_ocp_probe(device_t);
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static struct resource *pci_ocp_alloc_resource(device_t, device_t, int, int *,
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u_long, u_long, u_long, u_int);
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static int pci_ocp_read_ivar(device_t, device_t, int, uintptr_t *);
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static int pci_ocp_release_resource(device_t, device_t, int, int,
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struct resource *);
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static int pci_ocp_write_ivar(device_t, device_t, int, uintptr_t);
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static int pci_ocp_maxslots(device_t);
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static uint32_t pci_ocp_read_config(device_t, u_int, u_int, u_int, u_int, int);
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static void pci_ocp_write_config(device_t, u_int, u_int, u_int, u_int,
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uint32_t, int);
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/*
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* Bus interface definitions.
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*/
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static device_method_t pci_ocp_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, pci_ocp_probe),
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DEVMETHOD(device_attach, pci_ocp_attach),
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/* Bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_read_ivar, pci_ocp_read_ivar),
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DEVMETHOD(bus_write_ivar, pci_ocp_write_ivar),
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DEVMETHOD(bus_alloc_resource, pci_ocp_alloc_resource),
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DEVMETHOD(bus_release_resource, pci_ocp_release_resource),
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DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
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DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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/* pcib interface */
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DEVMETHOD(pcib_maxslots, pci_ocp_maxslots),
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DEVMETHOD(pcib_read_config, pci_ocp_read_config),
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DEVMETHOD(pcib_write_config, pci_ocp_write_config),
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DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
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{ 0, 0 }
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};
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static driver_t pci_ocp_driver = {
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"pcib",
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pci_ocp_methods,
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sizeof(struct pci_ocp_softc),
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};
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devclass_t pcib_devclass;
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DRIVER_MODULE(pcib, ocpbus, pci_ocp_driver, pcib_devclass, 0, 0);
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static uint32_t
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pci_ocp_cfgread(struct pci_ocp_softc *sc, u_int bus, u_int slot, u_int func,
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u_int reg, int bytes)
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{
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uint32_t addr, data;
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if (bus == sc->sc_busnr)
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bus = 0;
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addr = CONFIG_ACCESS_ENABLE;
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addr |= (bus & 0xff) << 16;
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addr |= (slot & 0x1f) << 11;
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addr |= (func & 0x7) << 8;
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addr |= reg & 0xfc;
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if (sc->sc_pcie_cap)
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addr |= (reg & 0xf00) << 16;
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
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switch (bytes) {
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case 1:
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data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
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REG_CFG_DATA + (reg & 3));
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break;
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case 2:
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data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
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REG_CFG_DATA + (reg & 2)));
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break;
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case 4:
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data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
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REG_CFG_DATA));
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break;
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default:
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data = ~0;
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break;
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}
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return (data);
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}
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static void
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pci_ocp_cfgwrite(struct pci_ocp_softc *sc, u_int bus, u_int slot, u_int func,
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u_int reg, uint32_t data, int bytes)
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{
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uint32_t addr;
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if (bus == sc->sc_busnr)
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bus = 0;
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addr = CONFIG_ACCESS_ENABLE;
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addr |= (bus & 0xff) << 16;
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addr |= (slot & 0x1f) << 11;
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addr |= (func & 0x7) << 8;
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addr |= reg & 0xfc;
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if (sc->sc_pcie_cap)
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addr |= (reg & 0xf00) << 16;
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
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switch (bytes) {
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case 1:
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bus_space_write_1(sc->sc_bst, sc->sc_bsh,
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REG_CFG_DATA + (reg & 3), data);
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break;
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case 2:
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bus_space_write_2(sc->sc_bst, sc->sc_bsh,
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REG_CFG_DATA + (reg & 2), htole16(data));
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break;
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case 4:
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bus_space_write_4(sc->sc_bst, sc->sc_bsh,
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REG_CFG_DATA, htole32(data));
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break;
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}
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}
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#if 0
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static void
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dump(struct pci_ocp_softc *sc)
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{
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unsigned int i;
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#define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o)
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for (i = 0; i < 5; i++) {
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printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i)));
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printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i)));
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printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i)));
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printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i)));
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}
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printf("\n");
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for (i = 1; i < 4; i++) {
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printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i)));
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printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i)));
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printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i)));
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printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i)));
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}
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printf("\n");
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#undef RD
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for (i = 0; i < 0x48; i += 4) {
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printf("cfg%02x=0x%08x\n", i, pci_ocp_cfgread(sc, 0, 0, 0,
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i, 4));
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}
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}
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#endif
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static int
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pci_ocp_maxslots(device_t dev)
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{
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struct pci_ocp_softc *sc = device_get_softc(dev);
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return ((sc->sc_pcie_cap) ? 0 : 31);
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}
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static uint32_t
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pci_ocp_read_config(device_t dev, u_int bus, u_int slot, u_int func,
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u_int reg, int bytes)
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{
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struct pci_ocp_softc *sc = device_get_softc(dev);
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u_int devfn;
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if (bus == sc->sc_busnr && !sc->sc_pcie_cap && slot < 10)
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return (~0);
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devfn = DEVFN(bus, slot, func);
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/*
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* For the host controller itself, pretend to be a standard
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* PCI bridge, rather than a PowerPC processor. That way the
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* generic PCI code will enumerate all subordinate busses
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* and devices as usual.
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*/
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if (sc->sc_pcie_cap && devfn == 0) {
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if (reg == PCIR_CLASS && bytes == 1)
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return (PCIC_BRIDGE);
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if (reg == PCIR_SUBCLASS && bytes == 1)
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return (PCIS_BRIDGE_PCI);
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}
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if (devfn == sc->sc_devfn_tundra)
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return (~0);
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if (devfn == sc->sc_devfn_via_ide && reg == PCIR_INTPIN)
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return (1);
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return (pci_ocp_cfgread(sc, bus, slot, func, reg, bytes));
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}
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static void
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pci_ocp_write_config(device_t dev, u_int bus, u_int slot, u_int func,
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u_int reg, uint32_t val, int bytes)
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{
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struct pci_ocp_softc *sc = device_get_softc(dev);
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if (bus == sc->sc_busnr && !sc->sc_pcie_cap && slot < 10)
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return;
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pci_ocp_cfgwrite(sc, bus, slot, func, reg, val, bytes);
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}
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static int
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pci_ocp_probe(device_t dev)
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{
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char buf[128];
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struct pci_ocp_softc *sc;
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const char *type;
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device_t parent;
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u_long start, size;
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uintptr_t devtype;
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uint32_t cfgreg;
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uint8_t capptr;
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int error;
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parent = device_get_parent(dev);
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error = BUS_READ_IVAR(parent, dev, OCPBUS_IVAR_DEVTYPE, &devtype);
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if (error)
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return (error);
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if (devtype != OCPBUS_DEVTYPE_PCIB)
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return (ENXIO);
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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sc->sc_rid = 0;
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sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
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RF_ACTIVE);
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if (sc->sc_res == NULL)
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return (ENXIO);
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sc->sc_bst = rman_get_bustag(sc->sc_res);
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sc->sc_bsh = rman_get_bushandle(sc->sc_res);
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sc->sc_busnr = 0;
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error = ENOENT;
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cfgreg = pci_ocp_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2);
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if (cfgreg != 0x1057 && cfgreg != 0x1957)
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goto out;
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cfgreg = pci_ocp_cfgread(sc, 0, 0, 0, PCIR_CLASS, 1);
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if (cfgreg != PCIC_PROCESSOR)
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goto out;
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cfgreg = pci_ocp_cfgread(sc, 0, 0, 0, PCIR_SUBCLASS, 1);
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if (cfgreg != PCIS_PROCESSOR_POWERPC)
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goto out;
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cfgreg = pci_ocp_cfgread(sc, 0, 0, 0, PCIR_PROGIF, 1);
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if (cfgreg != 0) /* RC mode = 0, EP mode = 1 */
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goto out;
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type = "PCI";
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capptr = pci_ocp_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1);
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while (capptr != 0) {
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cfgreg = pci_ocp_cfgread(sc, 0, 0, 0, capptr, 2);
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switch (cfgreg & 0xff) {
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case PCIY_PCIX: /* PCI-X */
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type = "PCI-X";
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break;
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case PCIY_EXPRESS: /* PCI Express */
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type = "PCI Express";
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sc->sc_pcie_cap = capptr;
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break;
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}
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capptr = (cfgreg >> 8) & 0xff;
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}
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error = bus_get_resource(dev, SYS_RES_MEMORY, 1, &start, &size);
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if (error || start == 0 || size == 0)
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goto out;
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snprintf(buf, sizeof(buf),
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"Freescale on-chip %s host controller", type);
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device_set_desc_copy(dev, buf);
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error = BUS_PROBE_DEFAULT;
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out:
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bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res);
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return (error);
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}
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static void
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pci_ocp_init_via(struct pci_ocp_softc *sc, uint16_t device, int bus,
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int slot, int fn)
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{
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if (device == 0x0686) {
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pci_ocp_write_config(sc->sc_dev, bus, slot, fn, 0x52, 0x34, 1);
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pci_ocp_write_config(sc->sc_dev, bus, slot, fn, 0x77, 0x00, 1);
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pci_ocp_write_config(sc->sc_dev, bus, slot, fn, 0x83, 0x98, 1);
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pci_ocp_write_config(sc->sc_dev, bus, slot, fn, 0x85, 0x03, 1);
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} else if (device == 0x0571) {
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sc->sc_devfn_via_ide = DEVFN(bus, slot, fn);
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pci_ocp_write_config(sc->sc_dev, bus, slot, fn, 0x40, 0x0b, 1);
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}
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}
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static int
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pci_ocp_init_bar(struct pci_ocp_softc *sc, int bus, int slot, int func,
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int barno)
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{
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bus_addr_t *allocp;
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uint32_t addr, mask, size;
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int reg, width;
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reg = PCIR_BAR(barno);
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if (DEVFN(bus, slot, func) == sc->sc_devfn_via_ide) {
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switch (barno) {
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case 0: addr = 0x1f0; break;
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case 1: addr = 0x3f4; break;
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case 2: addr = 0x170; break;
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case 3: addr = 0x374; break;
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case 4: addr = 0xcc0; break;
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default: return (1);
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}
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pci_ocp_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
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return (1);
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}
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pci_ocp_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
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size = pci_ocp_read_config(sc->sc_dev, bus, slot, func, reg, 4);
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if (size == 0)
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return (1);
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width = ((size & 7) == 4) ? 2 : 1;
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if (size & 1) { /* I/O port */
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allocp = &sc->sc_ioport_alloc;
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size &= ~3;
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if ((size & 0xffff0000) == 0)
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size |= 0xffff0000;
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} else { /* memory */
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allocp = &sc->sc_iomem_alloc;
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size &= ~15;
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}
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mask = ~size;
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size = mask + 1;
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/* Sanity check (must be a power of 2). */
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if (size & mask)
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return (width);
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addr = (*allocp + mask) & ~mask;
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*allocp = addr + size;
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if (bootverbose)
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printf("PCI %u:%u:%u:%u: reg %x: size=%08x: addr=%08x\n",
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device_get_unit(sc->sc_dev), bus, slot, func, reg,
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size, addr);
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|
|
pci_ocp_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
|
|
if (width == 2)
|
|
pci_ocp_write_config(sc->sc_dev, bus, slot, func, reg + 4,
|
|
0, 4);
|
|
return (width);
|
|
}
|
|
|
|
static u_int
|
|
pci_ocp_route_int(struct pci_ocp_softc *sc, u_int bus, u_int slot, u_int func,
|
|
u_int intpin)
|
|
{
|
|
u_int devfn, intline;
|
|
|
|
devfn = DEVFN(bus, slot, func);
|
|
if (devfn == sc->sc_devfn_via_ide)
|
|
intline = 14;
|
|
else if (devfn == sc->sc_devfn_via_ide + 1)
|
|
intline = 10;
|
|
else if (devfn == sc->sc_devfn_via_ide + 2)
|
|
intline = 10;
|
|
else {
|
|
if (intpin != 0) {
|
|
intline = intpin - 1;
|
|
intline += (bus != sc->sc_busnr) ? slot : 0;
|
|
intline = PIC_IRQ_EXT(intline & 3);
|
|
} else
|
|
intline = 0xff;
|
|
}
|
|
|
|
if (bootverbose)
|
|
printf("PCI %u:%u:%u:%u: intpin %u: intline=%u\n",
|
|
device_get_unit(sc->sc_dev), bus, slot, func,
|
|
intpin, intline);
|
|
|
|
return (intline);
|
|
}
|
|
|
|
static int
|
|
pci_ocp_init(struct pci_ocp_softc *sc, int bus, int nslots)
|
|
{
|
|
int secbus, slot;
|
|
int func, maxfunc;
|
|
int bar, maxbar;
|
|
uint16_t vendor, device;
|
|
uint8_t command, hdrtype, class, subclass;
|
|
uint8_t intline, intpin;
|
|
|
|
secbus = bus;
|
|
for (slot = 0; slot < nslots; slot++) {
|
|
maxfunc = 0;
|
|
for (func = 0; func <= maxfunc; func++) {
|
|
hdrtype = pci_ocp_read_config(sc->sc_dev, bus, slot,
|
|
func, PCIR_HDRTYPE, 1);
|
|
if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
|
|
continue;
|
|
|
|
if (func == 0 && (hdrtype & PCIM_MFDEV))
|
|
maxfunc = PCI_FUNCMAX;
|
|
|
|
vendor = pci_ocp_read_config(sc->sc_dev, bus, slot,
|
|
func, PCIR_VENDOR, 2);
|
|
device = pci_ocp_read_config(sc->sc_dev, bus, slot,
|
|
func, PCIR_DEVICE, 2);
|
|
|
|
if (vendor == 0x1957 && device == 0x3fff) {
|
|
sc->sc_devfn_tundra = DEVFN(bus, slot, func);
|
|
continue;
|
|
}
|
|
|
|
command = pci_ocp_read_config(sc->sc_dev, bus, slot,
|
|
func, PCIR_COMMAND, 1);
|
|
command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
|
|
pci_ocp_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_COMMAND, command, 1);
|
|
|
|
if (vendor == 0x1106)
|
|
pci_ocp_init_via(sc, device, bus, slot, func);
|
|
|
|
/* Program the base address registers. */
|
|
maxbar = (hdrtype & PCIM_HDRTYPE) ? 1 : 6;
|
|
bar = 0;
|
|
while (bar < maxbar)
|
|
bar += pci_ocp_init_bar(sc, bus, slot, func,
|
|
bar);
|
|
|
|
/* Perform interrupt routing. */
|
|
intpin = pci_ocp_read_config(sc->sc_dev, bus, slot,
|
|
func, PCIR_INTPIN, 1);
|
|
intline = pci_ocp_route_int(sc, bus, slot, func,
|
|
intpin);
|
|
pci_ocp_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_INTLINE, intline, 1);
|
|
|
|
command |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
|
|
pci_ocp_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_COMMAND, command, 1);
|
|
|
|
/*
|
|
* Handle PCI-PCI bridges
|
|
*/
|
|
class = pci_ocp_read_config(sc->sc_dev, bus, slot,
|
|
func, PCIR_CLASS, 1);
|
|
if (class != PCIC_BRIDGE)
|
|
continue;
|
|
subclass = pci_ocp_read_config(sc->sc_dev, bus, slot,
|
|
func, PCIR_SUBCLASS, 1);
|
|
if (subclass != PCIS_BRIDGE_PCI)
|
|
continue;
|
|
|
|
secbus++;
|
|
|
|
/* Program I/O decoder. */
|
|
pci_ocp_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_IOBASEL_1, sc->sc_ioport.rm_start >> 8, 1);
|
|
pci_ocp_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_IOLIMITL_1, sc->sc_ioport.rm_end >> 8, 1);
|
|
pci_ocp_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_IOBASEH_1, sc->sc_ioport.rm_start >> 16, 2);
|
|
pci_ocp_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_IOLIMITH_1, sc->sc_ioport.rm_end >> 16, 2);
|
|
|
|
/* Program (non-prefetchable) memory decoder. */
|
|
pci_ocp_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_MEMBASE_1, sc->sc_iomem.rm_start >> 16, 2);
|
|
pci_ocp_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_MEMLIMIT_1, sc->sc_iomem.rm_end >> 16, 2);
|
|
|
|
/* Program prefetchable memory decoder. */
|
|
pci_ocp_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_PMBASEL_1, 0x0010, 2);
|
|
pci_ocp_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_PMLIMITL_1, 0x000f, 2);
|
|
pci_ocp_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_PMBASEH_1, 0x00000000, 4);
|
|
pci_ocp_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_PMLIMITH_1, 0x00000000, 4);
|
|
|
|
pci_ocp_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_PRIBUS_1, bus, 1);
|
|
pci_ocp_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_SECBUS_1, secbus, 1);
|
|
pci_ocp_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_SUBBUS_1, 0xff, 1);
|
|
|
|
secbus = pci_ocp_init(sc, secbus,
|
|
(subclass == PCIS_BRIDGE_PCI) ? 32 : 1);
|
|
|
|
pci_ocp_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_SUBBUS_1, secbus, 1);
|
|
}
|
|
}
|
|
|
|
return (secbus);
|
|
}
|
|
|
|
static void
|
|
pci_ocp_inbound(struct pci_ocp_softc *sc, int wnd, int tgt, u_long start,
|
|
u_long size, u_long pci_start)
|
|
{
|
|
uint32_t attr, bar, tar;
|
|
|
|
KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__));
|
|
|
|
switch (tgt) {
|
|
case OCP85XX_TGTIF_RAM1:
|
|
attr = 0xa0f55000 | (ffsl(size) - 2);
|
|
break;
|
|
default:
|
|
attr = 0;
|
|
break;
|
|
}
|
|
tar = start >> 12;
|
|
bar = pci_start >> 12;
|
|
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr);
|
|
}
|
|
|
|
static void
|
|
pci_ocp_outbound(struct pci_ocp_softc *sc, int wnd, int res, u_long start,
|
|
u_long size, u_long pci_start)
|
|
{
|
|
uint32_t attr, bar, tar;
|
|
|
|
switch (res) {
|
|
case SYS_RES_MEMORY:
|
|
attr = 0x80044000 | (ffsl(size) - 2);
|
|
break;
|
|
case SYS_RES_IOPORT:
|
|
attr = 0x80088000 | (ffsl(size) - 2);
|
|
break;
|
|
default:
|
|
attr = 0x0004401f;
|
|
break;
|
|
}
|
|
bar = start >> 12;
|
|
tar = pci_start >> 12;
|
|
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr);
|
|
}
|
|
|
|
static int
|
|
pci_ocp_iorange(struct pci_ocp_softc *sc, int type, int wnd)
|
|
{
|
|
struct rman *rm;
|
|
u_long start, end, size, alloc;
|
|
bus_addr_t pci_start, pci_end;
|
|
bus_addr_t *vap, *allocp;
|
|
int error;
|
|
|
|
error = bus_get_resource(sc->sc_dev, type, 1, &start, &size);
|
|
if (error)
|
|
return (error);
|
|
|
|
end = start + size - 1;
|
|
|
|
switch (type) {
|
|
case SYS_RES_IOPORT:
|
|
rm = &sc->sc_ioport;
|
|
pci_start = 0x0000;
|
|
pci_end = 0xffff;
|
|
alloc = 0x1000;
|
|
vap = &sc->sc_ioport_va;
|
|
allocp = &sc->sc_ioport_alloc;
|
|
break;
|
|
case SYS_RES_MEMORY:
|
|
rm = &sc->sc_iomem;
|
|
pci_start = start;
|
|
pci_end = end;
|
|
alloc = 0;
|
|
vap = &sc->sc_iomem_va;
|
|
allocp = &sc->sc_iomem_alloc;
|
|
break;
|
|
default:
|
|
return (EINVAL);
|
|
}
|
|
|
|
rm->rm_type = RMAN_ARRAY;
|
|
rm->rm_start = pci_start;
|
|
rm->rm_end = pci_end;
|
|
error = rman_init(rm);
|
|
if (error)
|
|
return (error);
|
|
|
|
error = rman_manage_region(rm, pci_start, pci_end);
|
|
if (error) {
|
|
rman_fini(rm);
|
|
return (error);
|
|
}
|
|
|
|
*allocp = pci_start + alloc;
|
|
*vap = (uintptr_t)pmap_mapdev(start, size);
|
|
if (wnd != -1)
|
|
pci_ocp_outbound(sc, wnd, type, start, size, pci_start);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
pci_ocp_attach(device_t dev)
|
|
{
|
|
struct pci_ocp_softc *sc;
|
|
uint32_t cfgreg;
|
|
int error, nslots;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->sc_dev = dev;
|
|
|
|
sc->sc_rid = 0;
|
|
sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
|
|
RF_ACTIVE);
|
|
if (sc->sc_res == NULL) {
|
|
device_printf(dev, "could not map I/O memory\n");
|
|
return (ENXIO);
|
|
}
|
|
sc->sc_bst = rman_get_bustag(sc->sc_res);
|
|
sc->sc_bsh = rman_get_bushandle(sc->sc_res);
|
|
|
|
cfgreg = pci_ocp_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2);
|
|
cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
|
|
PCIM_CMD_PORTEN;
|
|
pci_ocp_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2);
|
|
|
|
pci_ocp_outbound(sc, 0, -1, 0, 0, 0);
|
|
error = pci_ocp_iorange(sc, SYS_RES_MEMORY, 1);
|
|
error = pci_ocp_iorange(sc, SYS_RES_IOPORT, 2);
|
|
pci_ocp_outbound(sc, 3, -1, 0, 0, 0);
|
|
pci_ocp_outbound(sc, 4, -1, 0, 0, 0);
|
|
|
|
pci_ocp_inbound(sc, 1, -1, 0, 0, 0);
|
|
pci_ocp_inbound(sc, 2, -1, 0, 0, 0);
|
|
pci_ocp_inbound(sc, 3, OCP85XX_TGTIF_RAM1, 0, 2U*1024U*1024U*1024U, 0);
|
|
|
|
sc->sc_devfn_tundra = -1;
|
|
sc->sc_devfn_via_ide = -1;
|
|
|
|
/*
|
|
* PCI Express host controllers require a link. We don't
|
|
* fail the attach if there's no link, but we also don't
|
|
* create a child pci(4) device.
|
|
*/
|
|
if (sc->sc_pcie_cap) {
|
|
cfgreg = pci_ocp_cfgread(sc, 0, 0, 0, PCIR_FSL_LTSSM, 4);
|
|
if (cfgreg < FSL_LTSSM_L0)
|
|
return (0);
|
|
}
|
|
|
|
nslots = (sc->sc_pcie_cap) ? 1 : 32;
|
|
pci_ocp_init(sc, sc->sc_busnr, nslots);
|
|
|
|
device_add_child(dev, "pci", -1);
|
|
return (bus_generic_attach(dev));
|
|
}
|
|
|
|
static struct resource *
|
|
pci_ocp_alloc_resource(device_t dev, device_t child, int type, int *rid,
|
|
u_long start, u_long end, u_long count, u_int flags)
|
|
{
|
|
struct pci_ocp_softc *sc = device_get_softc(dev);
|
|
struct rman *rm;
|
|
struct resource *res;
|
|
bus_addr_t va;
|
|
|
|
switch (type) {
|
|
case SYS_RES_IOPORT:
|
|
rm = &sc->sc_ioport;
|
|
va = sc->sc_ioport_va;
|
|
break;
|
|
case SYS_RES_MEMORY:
|
|
rm = &sc->sc_iomem;
|
|
va = sc->sc_iomem_va;
|
|
break;
|
|
case SYS_RES_IRQ:
|
|
if (start < PIC_IRQ_START) {
|
|
device_printf(dev, "%s requested ISA interrupt %lu\n",
|
|
device_get_nameunit(child), start);
|
|
}
|
|
flags |= RF_SHAREABLE;
|
|
return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
|
|
type, rid, start, end, count, flags));
|
|
default:
|
|
return (NULL);
|
|
}
|
|
|
|
res = rman_reserve_resource(rm, start, end, count, flags, child);
|
|
if (res == NULL)
|
|
return (NULL);
|
|
|
|
rman_set_bustag(res, &bs_le_tag);
|
|
rman_set_bushandle(res, va + rman_get_start(res) - rm->rm_start);
|
|
return (res);
|
|
}
|
|
|
|
static int
|
|
pci_ocp_release_resource(device_t dev, device_t child, int type, int rid,
|
|
struct resource *res)
|
|
{
|
|
|
|
return (rman_release_resource(res));
|
|
}
|
|
|
|
static int
|
|
pci_ocp_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
|
|
{
|
|
struct pci_ocp_softc *sc = device_get_softc(dev);
|
|
|
|
switch (which) {
|
|
case PCIB_IVAR_BUS:
|
|
*result = sc->sc_busnr;
|
|
return (0);
|
|
case PCIB_IVAR_DOMAIN:
|
|
*result = device_get_unit(dev);
|
|
return (0);
|
|
}
|
|
return (ENOENT);
|
|
}
|
|
|
|
static int
|
|
pci_ocp_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
|
|
{
|
|
struct pci_ocp_softc *sc = device_get_softc(dev);
|
|
|
|
switch (which) {
|
|
case PCIB_IVAR_BUS:
|
|
sc->sc_busnr = value;
|
|
return (0);
|
|
}
|
|
return (ENOENT);
|
|
}
|