dc4ee6ca91
make use of it where possible. This primarily brings in support for newer hardware, and FreeBSD is not yet able to support the abundance of IRQs on new hardware and many features in the Ethernet driver. Because of the changes to IRQs in the Simple Executive, we have to maintain our own list of Octeon IRQs now, which probably can be pared-down and be specific to the CIU interrupt unit soon, and when other interrupt mechanisms are added they can maintain their own definitions. Remove unmasking of interrupts from within the UART device now that the function used is no longer present in the Simple Executive. The unmasking seems to have been gratuitous as this is more properly handled by the buses above the UART device, and seems to work on that basis.
189 lines
9.5 KiB
C
189 lines
9.5 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* Module to support operations on core such as TLB config, etc.
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*
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* <hr>$Revision: 70030 $<hr>
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*
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*/
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#ifndef __CVMX_CORE_H__
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#define __CVMX_CORE_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* The types of performance counters supported per cpu
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*/
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typedef enum
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{
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CVMX_CORE_PERF_NONE = 0, /**< Turn off the performance counter */
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CVMX_CORE_PERF_CLK = 1, /**< Conditionally clocked cycles (as opposed to count/cvm_count which count even with no clocks) */
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CVMX_CORE_PERF_ISSUE = 2, /**< Instructions issued but not retired */
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CVMX_CORE_PERF_RET = 3, /**< Instructions retired */
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CVMX_CORE_PERF_NISSUE = 4, /**< Cycles no issue */
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CVMX_CORE_PERF_SISSUE = 5, /**< Cycles single issue */
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CVMX_CORE_PERF_DISSUE = 6, /**< Cycles dual issue */
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CVMX_CORE_PERF_IFI = 7, /**< Cycle ifetch issued (but not necessarily commit to pp_mem) */
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CVMX_CORE_PERF_BR = 8, /**< Branches retired */
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CVMX_CORE_PERF_BRMIS = 9, /**< Branch mispredicts */
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CVMX_CORE_PERF_J = 10, /**< Jumps retired */
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CVMX_CORE_PERF_JMIS = 11, /**< Jumps mispredicted */
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CVMX_CORE_PERF_REPLAY = 12, /**< Mem Replays */
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CVMX_CORE_PERF_IUNA = 13, /**< Cycles idle due to unaligned_replays */
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CVMX_CORE_PERF_TRAP = 14, /**< trap_6a signal */
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CVMX_CORE_PERF_UULOAD = 16, /**< Unexpected unaligned loads (REPUN=1) */
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CVMX_CORE_PERF_UUSTORE = 17, /**< Unexpected unaligned store (REPUN=1) */
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CVMX_CORE_PERF_ULOAD = 18, /**< Unaligned loads (REPUN=1 or USEUN=1) */
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CVMX_CORE_PERF_USTORE = 19, /**< Unaligned store (REPUN=1 or USEUN=1) */
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CVMX_CORE_PERF_EC = 20, /**< Exec clocks(must set CvmCtl[DISCE] for accurate timing) */
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CVMX_CORE_PERF_MC = 21, /**< Mul clocks(must set CvmCtl[DISCE] for accurate timing) */
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CVMX_CORE_PERF_CC = 22, /**< Crypto clocks(must set CvmCtl[DISCE] for accurate timing) */
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CVMX_CORE_PERF_CSRC = 23, /**< Issue_csr clocks(must set CvmCtl[DISCE] for accurate timing) */
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CVMX_CORE_PERF_CFETCH = 24, /**< Icache committed fetches (demand+prefetch) */
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CVMX_CORE_PERF_CPREF = 25, /**< Icache committed prefetches */
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CVMX_CORE_PERF_ICA = 26, /**< Icache aliases */
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CVMX_CORE_PERF_II = 27, /**< Icache invalidates */
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CVMX_CORE_PERF_IP = 28, /**< Icache parity error */
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CVMX_CORE_PERF_CIMISS = 29, /**< Cycles idle due to imiss (must set CvmCtl[DISCE] for accurate timing) */
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CVMX_CORE_PERF_WBUF = 32, /**< Number of write buffer entries created */
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CVMX_CORE_PERF_WDAT = 33, /**< Number of write buffer data cycles used (may need to set CvmCtl[DISCE] for accurate counts) */
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CVMX_CORE_PERF_WBUFLD = 34, /**< Number of write buffer entries forced out by loads */
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CVMX_CORE_PERF_WBUFFL = 35, /**< Number of cycles that there was no available write buffer entry (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) */
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CVMX_CORE_PERF_WBUFTR = 36, /**< Number of stores that found no available write buffer entries */
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CVMX_CORE_PERF_BADD = 37, /**< Number of address bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) */
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CVMX_CORE_PERF_BADDL2 = 38, /**< Number of address bus cycles not reflected (i.e. destined for L2) (may need to set CvmCtl[DISCE] for accurate counts) */
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CVMX_CORE_PERF_BFILL = 39, /**< Number of fill bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) */
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CVMX_CORE_PERF_DDIDS = 40, /**< Number of Dstream DIDs created */
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CVMX_CORE_PERF_IDIDS = 41, /**< Number of Istream DIDs created */
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CVMX_CORE_PERF_DIDNA = 42, /**< Number of cycles that no DIDs were available (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) */
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CVMX_CORE_PERF_LDS = 43, /**< Number of load issues */
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CVMX_CORE_PERF_LMLDS = 44, /**< Number of local memory load */
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CVMX_CORE_PERF_IOLDS = 45, /**< Number of I/O load issues */
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CVMX_CORE_PERF_DMLDS = 46, /**< Number of loads that were not prefetches and missed in the cache */
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CVMX_CORE_PERF_STS = 48, /**< Number of store issues */
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CVMX_CORE_PERF_LMSTS = 49, /**< Number of local memory store issues */
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CVMX_CORE_PERF_IOSTS = 50, /**< Number of I/O store issues */
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CVMX_CORE_PERF_IOBDMA = 51, /**< Number of IOBDMAs */
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CVMX_CORE_PERF_DTLB = 53, /**< Number of dstream TLB refill, invalid, or modified exceptions */
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CVMX_CORE_PERF_DTLBAD = 54, /**< Number of dstream TLB address errors */
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CVMX_CORE_PERF_ITLB = 55, /**< Number of istream TLB refill, invalid, or address error exceptions */
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CVMX_CORE_PERF_SYNC = 56, /**< Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */
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CVMX_CORE_PERF_SYNCIOB = 57, /**< Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */
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CVMX_CORE_PERF_SYNCW = 58, /**< Number of SYNCWs */
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/* Added in CN63XX */
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CVMX_CORE_PERF_ERETMIS = 64, /**< D/eret mispredicts */
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CVMX_CORE_PERF_LIKMIS = 65, /**< Branch likely mispredicts */
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CVMX_CORE_PERF_HAZTR = 66, /**< Hazard traps due to *MTC0 to CvmCtl, Perf counter control, EntryHi, or CvmMemCtl registers */
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CVMX_CORE_PERF_MAX /**< This not a counter, just a marker for the highest number */
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} cvmx_core_perf_t;
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/**
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* Bit description of the COP0 counter control register
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*/
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typedef union
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{
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uint32_t u32;
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struct
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{
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#ifdef __BIG_ENDIAN_BITFIELD
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uint32_t m : 1; /**< Set to 1 for sel 0 and 0 for sel 2, indicating there are two performance counters */
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uint32_t w : 1; /**< Set to 1 indicating counters are 64 bit */
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uint32_t reserved_11_29 :15;
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cvmx_core_perf_t event :10; /**< Selects the event to be counted by the corresponding Counter Register */
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uint32_t ie : 1; /**< Interrupt Enable */
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uint32_t u : 1; /**< Count in user mode */
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uint32_t s : 1; /**< Count in supervisor mode */
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uint32_t k : 1; /**< Count in kernel mode */
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uint32_t ex : 1; /**< Count in exception context */
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#else
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uint32_t ex : 1;
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uint32_t k : 1;
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uint32_t s : 1;
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uint32_t u : 1;
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uint32_t ie : 1;
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uint32_t event :10;
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uint32_t reserved_11_29 :15;
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uint32_t w : 1;
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uint32_t m : 1;
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#endif
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} s;
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} cvmx_core_perf_control_t;
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typedef enum {
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CVMX_TLB_PAGEMASK_4K = 0x3 << 11,
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CVMX_TLB_PAGEMASK_16K = 0xF << 11,
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CVMX_TLB_PAGEMASK_64K = 0x3F << 11,
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CVMX_TLB_PAGEMASK_256K = 0xFF << 11,
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CVMX_TLB_PAGEMASK_1M = 0x3FF << 11,
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CVMX_TLB_PAGEMASK_4M = 0xFFF << 11,
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CVMX_TLB_PAGEMASK_16M = 0x3FFF << 11,
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CVMX_TLB_PAGEMASK_64M = 0xFFFF << 11,
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CVMX_TLB_PAGEMASK_256M = 0x3FFFF << 11,
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} cvmx_tlb_pagemask_t;
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int cvmx_core_add_wired_tlb_entry(uint64_t hi, uint64_t lo0, uint64_t lo1, cvmx_tlb_pagemask_t page_mask);
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int cvmx_core_add_fixed_tlb_mapping(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask);
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int cvmx_core_add_fixed_tlb_mapping_bits(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask);
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/**
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* Return number of TLB entries.
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*/
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int cvmx_core_get_tlb_entries(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CVMX_CORE_H__ */
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