0f34084f95
mmc(4). For the most part, this consists of support for:
- Switching the signal voltage (VCCQ) to 1.8 V or (if supported
by the host controller) to 1.2 V,
- setting the UHS mode as appropriate in the SDHCI_HOST_CONTROL2
register,
- setting the power class in the eMMC device according to the
core supply voltage (VCC),
- using different bits for enabling a bus width of 4 and 8 bits
in the the eMMC device at DDR or higher timings respectively,
- arbitrating timings faster than high speed if there actually
are additional devices on the same MMC bus.
Given that support for DDR52 is not denoted by SDHCI capability
registers, availability of that timing is indicated by a new
quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI
controllers so far. Generally, what it takes for a sdhci(4)
front-end to enable support for DDR52 is to hook up the bridge
method mmcbr_switch_vccq (which especially for 1.2 V signaling
support is chip/board specific) and the sdhci_set_uhs_timing
sdhci(4) method.
As a side-effect, this change also fixes communication with
some eMMC devices at SDR high speed mode with 52 MHz due to
the signaling voltage and UHS bits in the SDHCI controller no
longer being left in an inappropriate state.
Compared to 52 MHz at SDR high speed which typically yields
~45 MB/s with the eMMC chips tested, throughput goes up to
~80 MB/s at DDR52.
Additionally, this change already adds infrastructure and quite
some code for modes up to HS400ES and SDR104 respectively (I did
not want to add to much stuff at a time, though). Essentially,
what is still missing in order to be able to activate support
for these latter is is support for and handling of (re-)tuning.
o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as
hw.sdhci.quirk_set, which (when hooked up in the front-end)
allow to set/clear sdhci(4) quirks for debugging and testing
purposes. However, especially for SDHCI controllers on the
PCI bus which have no specific support code so far and, thus,
are picked up as generic SDHCI controllers, hw.sdhci.quirk_set
allows for setting the necessary quirks (if required).
o In mmc(4), check and handle the return values of some more
function calls instead of assuming that everything went right.
In case failures actually are not problematic, indicate that
by casting the return value to void.
Reviewed by: jmcneill
519 lines
15 KiB
C
519 lines
15 KiB
C
/*-
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* Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <sys/taskqueue.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <dev/mmc/bridge.h>
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#include <dev/sdhci/sdhci.h>
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#include "mmcbr_if.h"
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#include "sdhci_if.h"
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/*
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* PCI registers
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*/
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#define PCI_SDHCI_IFPIO 0x00
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#define PCI_SDHCI_IFDMA 0x01
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#define PCI_SDHCI_IFVENDOR 0x02
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#define PCI_SLOT_INFO 0x40 /* 8 bits */
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#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1)
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#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7)
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/*
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* RICOH specific PCI registers
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*/
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#define SDHC_PCI_MODE_KEY 0xf9
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#define SDHC_PCI_MODE 0x150
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#define SDHC_PCI_MODE_SD20 0x10
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#define SDHC_PCI_BASE_FREQ_KEY 0xfc
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#define SDHC_PCI_BASE_FREQ 0xe1
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static const struct sdhci_device {
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uint32_t model;
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uint16_t subvendor;
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const char *desc;
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u_int quirks;
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} sdhci_devices[] = {
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{ 0x08221180, 0xffff, "RICOH R5C822 SD",
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SDHCI_QUIRK_FORCE_DMA },
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{ 0xe8221180, 0xffff, "RICOH R5CE822 SD",
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SDHCI_QUIRK_FORCE_DMA |
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SDHCI_QUIRK_LOWER_FREQUENCY },
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{ 0xe8231180, 0xffff, "RICOH R5CE823 SD",
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SDHCI_QUIRK_LOWER_FREQUENCY },
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{ 0x8034104c, 0xffff, "TI XX21/XX11 SD",
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SDHCI_QUIRK_FORCE_DMA },
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{ 0x05501524, 0xffff, "ENE CB712 SD",
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SDHCI_QUIRK_BROKEN_TIMINGS },
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{ 0x05511524, 0xffff, "ENE CB712 SD 2",
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SDHCI_QUIRK_BROKEN_TIMINGS },
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{ 0x07501524, 0xffff, "ENE CB714 SD",
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SDHCI_QUIRK_RESET_ON_IOS |
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SDHCI_QUIRK_BROKEN_TIMINGS },
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{ 0x07511524, 0xffff, "ENE CB714 SD 2",
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SDHCI_QUIRK_RESET_ON_IOS |
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SDHCI_QUIRK_BROKEN_TIMINGS },
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{ 0x410111ab, 0xffff, "Marvell CaFe SD",
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SDHCI_QUIRK_INCR_TIMEOUT_CONTROL },
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{ 0x2381197B, 0xffff, "JMicron JMB38X SD",
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SDHCI_QUIRK_32BIT_DMA_SIZE |
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SDHCI_QUIRK_RESET_AFTER_REQUEST },
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{ 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader",
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SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC },
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{ 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller",
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SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
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SDHCI_QUIRK_INTEL_POWER_UP_RESET |
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_MMC_DDR52 |
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SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
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SDHCI_QUIRK_PRESET_VALUE_BROKEN},
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{ 0x0f158086, 0xffff, "Intel Bay Trail SDXC Controller",
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_PRESET_VALUE_BROKEN },
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{ 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller",
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SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
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SDHCI_QUIRK_INTEL_POWER_UP_RESET |
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_MMC_DDR52 |
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SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
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SDHCI_QUIRK_PRESET_VALUE_BROKEN },
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{ 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller",
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SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
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SDHCI_QUIRK_DATA_TIMEOUT_1MHZ |
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SDHCI_QUIRK_INTEL_POWER_UP_RESET |
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_MMC_DDR52 |
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SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
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SDHCI_QUIRK_PRESET_VALUE_BROKEN },
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{ 0x22968086, 0xffff, "Intel Braswell SDXC Controller",
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_PRESET_VALUE_BROKEN },
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{ 0x5aca8086, 0xffff, "Intel Apollo Lake SDXC Controller",
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_PRESET_VALUE_BROKEN },
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{ 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller",
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SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
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SDHCI_QUIRK_INTEL_POWER_UP_RESET |
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_MMC_DDR52 |
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SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
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SDHCI_QUIRK_PRESET_VALUE_BROKEN },
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{ 0, 0xffff, NULL,
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0 }
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};
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struct sdhci_pci_softc {
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u_int quirks; /* Chip specific quirks */
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struct resource *irq_res; /* IRQ resource */
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void *intrhand; /* Interrupt handle */
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int num_slots; /* Number of slots on this controller */
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struct sdhci_slot slots[6];
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struct resource *mem_res[6]; /* Memory resource */
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uint8_t cfg_freq; /* Saved frequency */
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uint8_t cfg_mode; /* Saved mode */
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};
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static int sdhci_enable_msi = 1;
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SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi,
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0, "Enable MSI interrupts");
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static uint8_t
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sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
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{
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struct sdhci_pci_softc *sc = device_get_softc(dev);
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bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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return bus_read_1(sc->mem_res[slot->num], off);
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}
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static void
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sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off, uint8_t val)
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{
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struct sdhci_pci_softc *sc = device_get_softc(dev);
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bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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bus_write_1(sc->mem_res[slot->num], off, val);
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}
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static uint16_t
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sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
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{
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struct sdhci_pci_softc *sc = device_get_softc(dev);
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bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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return bus_read_2(sc->mem_res[slot->num], off);
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}
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static void
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sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off, uint16_t val)
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{
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struct sdhci_pci_softc *sc = device_get_softc(dev);
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bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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bus_write_2(sc->mem_res[slot->num], off, val);
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}
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static uint32_t
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sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
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{
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struct sdhci_pci_softc *sc = device_get_softc(dev);
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bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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return bus_read_4(sc->mem_res[slot->num], off);
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}
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static void
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sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off, uint32_t val)
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{
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struct sdhci_pci_softc *sc = device_get_softc(dev);
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bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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bus_write_4(sc->mem_res[slot->num], off, val);
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}
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static void
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sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off, uint32_t *data, bus_size_t count)
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{
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struct sdhci_pci_softc *sc = device_get_softc(dev);
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bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count);
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}
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static void
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sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot __unused,
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bus_size_t off, uint32_t *data, bus_size_t count)
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{
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struct sdhci_pci_softc *sc = device_get_softc(dev);
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bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count);
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}
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static void sdhci_pci_intr(void *arg);
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static void
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sdhci_lower_frequency(device_t dev)
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{
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struct sdhci_pci_softc *sc = device_get_softc(dev);
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/*
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* Enable SD2.0 mode.
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* NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822.
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*/
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pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
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sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1);
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pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1);
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pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
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/*
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* Some SD/MMC cards don't work with the default base
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* clock frequency of 200 MHz. Lower it to 50 MHz.
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*/
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pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
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sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1);
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pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1);
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pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
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}
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static void
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sdhci_restore_frequency(device_t dev)
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{
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struct sdhci_pci_softc *sc = device_get_softc(dev);
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/* Restore mode. */
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pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
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pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1);
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pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
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/* Restore frequency. */
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pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
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pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1);
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pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
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}
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static int
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sdhci_pci_probe(device_t dev)
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{
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uint32_t model;
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uint16_t subvendor;
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uint8_t class, subclass;
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int i, result;
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model = (uint32_t)pci_get_device(dev) << 16;
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model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
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subvendor = pci_get_subvendor(dev);
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class = pci_get_class(dev);
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subclass = pci_get_subclass(dev);
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result = ENXIO;
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for (i = 0; sdhci_devices[i].model != 0; i++) {
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if (sdhci_devices[i].model == model &&
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(sdhci_devices[i].subvendor == 0xffff ||
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sdhci_devices[i].subvendor == subvendor)) {
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device_set_desc(dev, sdhci_devices[i].desc);
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result = BUS_PROBE_DEFAULT;
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break;
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}
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}
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if (result == ENXIO && class == PCIC_BASEPERIPH &&
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subclass == PCIS_BASEPERIPH_SDHC) {
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device_set_desc(dev, "Generic SD HCI");
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result = BUS_PROBE_GENERIC;
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}
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return (result);
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}
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static int
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sdhci_pci_attach(device_t dev)
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{
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struct sdhci_pci_softc *sc = device_get_softc(dev);
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struct sdhci_slot *slot;
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uint32_t model;
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uint16_t subvendor;
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int bar, err, rid, slots, i;
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model = (uint32_t)pci_get_device(dev) << 16;
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model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
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subvendor = pci_get_subvendor(dev);
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/* Apply chip specific quirks. */
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for (i = 0; sdhci_devices[i].model != 0; i++) {
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if (sdhci_devices[i].model == model &&
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(sdhci_devices[i].subvendor == 0xffff ||
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sdhci_devices[i].subvendor == subvendor)) {
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sc->quirks = sdhci_devices[i].quirks;
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break;
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}
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}
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sc->quirks &= ~sdhci_quirk_clear;
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sc->quirks |= sdhci_quirk_set;
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/* Some controllers need to be bumped into the right mode. */
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if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
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sdhci_lower_frequency(dev);
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/* Read slots info from PCI registers. */
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slots = pci_read_config(dev, PCI_SLOT_INFO, 1);
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bar = PCI_SLOT_INFO_FIRST_BAR(slots);
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slots = PCI_SLOT_INFO_SLOTS(slots);
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if (slots > 6 || bar > 5) {
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device_printf(dev, "Incorrect slots information (%d, %d).\n",
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slots, bar);
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return (EINVAL);
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}
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/* Allocate IRQ. */
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i = 1;
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rid = 0;
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if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0)
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rid = 1;
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sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
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if (sc->irq_res == NULL) {
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device_printf(dev, "Can't allocate IRQ\n");
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pci_release_msi(dev);
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return (ENOMEM);
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}
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/* Scan all slots. */
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for (i = 0; i < slots; i++) {
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slot = &sc->slots[sc->num_slots];
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|
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/* Allocate memory. */
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rid = PCIR_BAR(bar + i);
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sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&rid, RF_ACTIVE);
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if (sc->mem_res[i] == NULL) {
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device_printf(dev,
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"Can't allocate memory for slot %d\n", i);
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continue;
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}
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|
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slot->quirks = sc->quirks;
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|
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if (sdhci_init_slot(dev, slot, i) != 0)
|
|
continue;
|
|
|
|
sc->num_slots++;
|
|
}
|
|
device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
|
|
/* Activate the interrupt */
|
|
err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
|
|
NULL, sdhci_pci_intr, sc, &sc->intrhand);
|
|
if (err)
|
|
device_printf(dev, "Can't setup IRQ\n");
|
|
pci_enable_busmaster(dev);
|
|
/* Process cards detection. */
|
|
for (i = 0; i < sc->num_slots; i++)
|
|
sdhci_start_slot(&sc->slots[i]);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
sdhci_pci_detach(device_t dev)
|
|
{
|
|
struct sdhci_pci_softc *sc = device_get_softc(dev);
|
|
int i;
|
|
|
|
bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
|
|
bus_release_resource(dev, SYS_RES_IRQ,
|
|
rman_get_rid(sc->irq_res), sc->irq_res);
|
|
pci_release_msi(dev);
|
|
|
|
for (i = 0; i < sc->num_slots; i++) {
|
|
sdhci_cleanup_slot(&sc->slots[i]);
|
|
bus_release_resource(dev, SYS_RES_MEMORY,
|
|
rman_get_rid(sc->mem_res[i]), sc->mem_res[i]);
|
|
}
|
|
if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
|
|
sdhci_restore_frequency(dev);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
sdhci_pci_shutdown(device_t dev)
|
|
{
|
|
struct sdhci_pci_softc *sc = device_get_softc(dev);
|
|
|
|
if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
|
|
sdhci_restore_frequency(dev);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
sdhci_pci_suspend(device_t dev)
|
|
{
|
|
struct sdhci_pci_softc *sc = device_get_softc(dev);
|
|
int i, err;
|
|
|
|
err = bus_generic_suspend(dev);
|
|
if (err)
|
|
return (err);
|
|
for (i = 0; i < sc->num_slots; i++)
|
|
sdhci_generic_suspend(&sc->slots[i]);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
sdhci_pci_resume(device_t dev)
|
|
{
|
|
struct sdhci_pci_softc *sc = device_get_softc(dev);
|
|
int i, err;
|
|
|
|
for (i = 0; i < sc->num_slots; i++)
|
|
sdhci_generic_resume(&sc->slots[i]);
|
|
err = bus_generic_resume(dev);
|
|
if (err)
|
|
return (err);
|
|
if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
|
|
sdhci_lower_frequency(dev);
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
sdhci_pci_intr(void *arg)
|
|
{
|
|
struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg;
|
|
int i;
|
|
|
|
for (i = 0; i < sc->num_slots; i++)
|
|
sdhci_generic_intr(&sc->slots[i]);
|
|
}
|
|
|
|
static device_method_t sdhci_methods[] = {
|
|
/* device_if */
|
|
DEVMETHOD(device_probe, sdhci_pci_probe),
|
|
DEVMETHOD(device_attach, sdhci_pci_attach),
|
|
DEVMETHOD(device_detach, sdhci_pci_detach),
|
|
DEVMETHOD(device_shutdown, sdhci_pci_shutdown),
|
|
DEVMETHOD(device_suspend, sdhci_pci_suspend),
|
|
DEVMETHOD(device_resume, sdhci_pci_resume),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
|
|
DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
|
|
|
|
/* mmcbr_if */
|
|
DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
|
|
DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq),
|
|
DEVMETHOD(mmcbr_request, sdhci_generic_request),
|
|
DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro),
|
|
DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
|
|
DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
|
|
|
|
/* SDHCI accessors */
|
|
DEVMETHOD(sdhci_read_1, sdhci_pci_read_1),
|
|
DEVMETHOD(sdhci_read_2, sdhci_pci_read_2),
|
|
DEVMETHOD(sdhci_read_4, sdhci_pci_read_4),
|
|
DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4),
|
|
DEVMETHOD(sdhci_write_1, sdhci_pci_write_1),
|
|
DEVMETHOD(sdhci_write_2, sdhci_pci_write_2),
|
|
DEVMETHOD(sdhci_write_4, sdhci_pci_write_4),
|
|
DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4),
|
|
DEVMETHOD(sdhci_set_uhs_timing, sdhci_generic_set_uhs_timing),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t sdhci_pci_driver = {
|
|
"sdhci_pci",
|
|
sdhci_methods,
|
|
sizeof(struct sdhci_pci_softc),
|
|
};
|
|
static devclass_t sdhci_pci_devclass;
|
|
|
|
DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL,
|
|
NULL);
|
|
MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1);
|
|
MMC_DECLARE_BRIDGE(sdhci_pci);
|