32d001e479
which is not complete. Likely, it was forgotten and not removed before committing.
1215 lines
28 KiB
C
1215 lines
28 KiB
C
/*-
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* Copyright (c) 2012-2014 Jakub Wojciech Klama <jceel@FreeBSD.org>.
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* Copyright (c) 2015 Svatopluk Kraus
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* Copyright (c) 2015 Michal Meloun
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* New-style Interrupt Framework
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*
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* TODO: - to support IPI (PPI) enabling on other CPUs if already started
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* - to complete things for removable PICs
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*/
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#include "opt_ddb.h"
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/syslog.h>
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#include <sys/malloc.h>
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#include <sys/proc.h>
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#include <sys/queue.h>
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#include <sys/bus.h>
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#include <sys/interrupt.h>
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#include <sys/conf.h>
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#include <sys/cpuset.h>
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#include <sys/sched.h>
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#include <sys/smp.h>
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#include <machine/atomic.h>
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#include <machine/intr.h>
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#include <machine/cpu.h>
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#include <machine/smp.h>
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#include <machine/stdarg.h>
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#ifdef FDT
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#endif
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#ifdef DDB
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#include <ddb/ddb.h>
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#endif
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#include "pic_if.h"
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#define INTRNAME_LEN (2*MAXCOMLEN + 1)
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#ifdef DEBUG
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#define debugf(fmt, args...) do { printf("%s(): ", __func__); \
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printf(fmt,##args); } while (0)
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#else
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#define debugf(fmt, args...)
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#endif
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MALLOC_DECLARE(M_INTRNG);
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MALLOC_DEFINE(M_INTRNG, "intr", "intr interrupt handling");
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/* Main interrupt handler called from assembler -> 'hidden' for C code. */
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void intr_irq_handler(struct trapframe *tf);
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/* Root interrupt controller stuff. */
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device_t intr_irq_root_dev;
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static intr_irq_filter_t *irq_root_filter;
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static void *irq_root_arg;
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static u_int irq_root_ipicount;
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/* Interrupt controller definition. */
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struct intr_pic {
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SLIST_ENTRY(intr_pic) pic_next;
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intptr_t pic_xref; /* hardware identification */
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device_t pic_dev;
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};
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static struct mtx pic_list_lock;
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static SLIST_HEAD(, intr_pic) pic_list;
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static struct intr_pic *pic_lookup(device_t dev, intptr_t xref);
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/* Interrupt source definition. */
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static struct mtx isrc_table_lock;
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static struct intr_irqsrc *irq_sources[NIRQ];
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u_int irq_next_free;
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#define IRQ_INVALID nitems(irq_sources)
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#ifdef SMP
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static boolean_t irq_assign_cpu = FALSE;
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#endif
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/*
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* - 2 counters for each I/O interrupt.
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* - MAXCPU counters for each IPI counters for SMP.
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*/
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#ifdef SMP
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#define INTRCNT_COUNT (NIRQ * 2 + INTR_IPI_COUNT * MAXCPU)
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#else
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#define INTRCNT_COUNT (NIRQ * 2)
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#endif
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/* Data for MI statistics reporting. */
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u_long intrcnt[INTRCNT_COUNT];
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char intrnames[INTRCNT_COUNT * INTRNAME_LEN];
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size_t sintrcnt = sizeof(intrcnt);
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size_t sintrnames = sizeof(intrnames);
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static u_int intrcnt_index;
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/*
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* Interrupt framework initialization routine.
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*/
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static void
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intr_irq_init(void *dummy __unused)
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{
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SLIST_INIT(&pic_list);
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mtx_init(&pic_list_lock, "intr pic list", NULL, MTX_DEF);
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mtx_init(&isrc_table_lock, "intr isrc table", NULL, MTX_DEF);
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}
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SYSINIT(intr_irq_init, SI_SUB_INTR, SI_ORDER_FIRST, intr_irq_init, NULL);
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static void
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intrcnt_setname(const char *name, int index)
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{
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snprintf(intrnames + INTRNAME_LEN * index, INTRNAME_LEN, "%-*s",
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INTRNAME_LEN - 1, name);
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}
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/*
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* Update name for interrupt source with interrupt event.
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*/
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static void
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intrcnt_updatename(struct intr_irqsrc *isrc)
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{
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/* QQQ: What about stray counter name? */
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mtx_assert(&isrc_table_lock, MA_OWNED);
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intrcnt_setname(isrc->isrc_event->ie_fullname, isrc->isrc_index);
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}
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/*
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* Virtualization for interrupt source interrupt counter increment.
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*/
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static inline void
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isrc_increment_count(struct intr_irqsrc *isrc)
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{
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/*
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* XXX - It should be atomic for PPI interrupts. It was proven that
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* the lost is measurable easily for timer PPI interrupts.
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*/
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isrc->isrc_count[0]++;
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/*atomic_add_long(&isrc->isrc_count[0], 1);*/
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}
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/*
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* Virtualization for interrupt source interrupt stray counter increment.
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*/
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static inline void
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isrc_increment_straycount(struct intr_irqsrc *isrc)
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{
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isrc->isrc_count[1]++;
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}
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/*
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* Virtualization for interrupt source interrupt name update.
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*/
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static void
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isrc_update_name(struct intr_irqsrc *isrc, const char *name)
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{
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char str[INTRNAME_LEN];
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mtx_assert(&isrc_table_lock, MA_OWNED);
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if (name != NULL) {
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snprintf(str, INTRNAME_LEN, "%s: %s", isrc->isrc_name, name);
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intrcnt_setname(str, isrc->isrc_index);
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snprintf(str, INTRNAME_LEN, "stray %s: %s", isrc->isrc_name,
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name);
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intrcnt_setname(str, isrc->isrc_index + 1);
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} else {
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snprintf(str, INTRNAME_LEN, "%s:", isrc->isrc_name);
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intrcnt_setname(str, isrc->isrc_index);
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snprintf(str, INTRNAME_LEN, "stray %s:", isrc->isrc_name);
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intrcnt_setname(str, isrc->isrc_index + 1);
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}
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}
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/*
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* Virtualization for interrupt source interrupt counters setup.
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*/
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static void
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isrc_setup_counters(struct intr_irqsrc *isrc)
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{
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u_int index;
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/*
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* XXX - it does not work well with removable controllers and
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* interrupt sources !!!
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*/
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index = atomic_fetchadd_int(&intrcnt_index, 2);
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isrc->isrc_index = index;
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isrc->isrc_count = &intrcnt[index];
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isrc_update_name(isrc, NULL);
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}
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#ifdef SMP
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/*
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* Virtualization for interrupt source IPI counters setup.
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*/
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u_long *
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intr_ipi_setup_counters(const char *name)
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{
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u_int index, i;
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char str[INTRNAME_LEN];
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index = atomic_fetchadd_int(&intrcnt_index, MAXCPU);
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for (i = 0; i < MAXCPU; i++) {
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snprintf(str, INTRNAME_LEN, "cpu%d:%s", i, name);
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intrcnt_setname(str, index + i);
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}
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return (&intrcnt[index]);
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}
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#endif
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/*
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* Main interrupt dispatch handler. It's called straight
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* from the assembler, where CPU interrupt is served.
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*/
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void
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intr_irq_handler(struct trapframe *tf)
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{
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struct trapframe * oldframe;
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struct thread * td;
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KASSERT(irq_root_filter != NULL, ("%s: no filter", __func__));
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PCPU_INC(cnt.v_intr);
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critical_enter();
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td = curthread;
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oldframe = td->td_intr_frame;
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td->td_intr_frame = tf;
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irq_root_filter(irq_root_arg);
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td->td_intr_frame = oldframe;
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critical_exit();
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}
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/*
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* interrupt controller dispatch function for interrupts. It should
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* be called straight from the interrupt controller, when associated interrupt
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* source is learned.
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*/
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void
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intr_irq_dispatch(struct intr_irqsrc *isrc, struct trapframe *tf)
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{
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KASSERT(isrc != NULL, ("%s: no source", __func__));
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isrc_increment_count(isrc);
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#ifdef INTR_SOLO
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if (isrc->isrc_filter != NULL) {
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int error;
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error = isrc->isrc_filter(isrc->isrc_arg, tf);
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PIC_POST_FILTER(isrc->isrc_dev, isrc);
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if (error == FILTER_HANDLED)
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return;
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} else
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#endif
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if (isrc->isrc_event != NULL) {
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if (intr_event_handle(isrc->isrc_event, tf) == 0)
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return;
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}
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isrc_increment_straycount(isrc);
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PIC_DISABLE_SOURCE(isrc->isrc_dev, isrc);
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device_printf(isrc->isrc_dev, "stray irq <%s> disabled",
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isrc->isrc_name);
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}
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/*
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* Allocate interrupt source.
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*/
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static struct intr_irqsrc *
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isrc_alloc(u_int type, u_int extsize)
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{
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struct intr_irqsrc *isrc;
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isrc = malloc(sizeof(*isrc) + extsize, M_INTRNG, M_WAITOK | M_ZERO);
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isrc->isrc_irq = IRQ_INVALID; /* just to be safe */
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isrc->isrc_type = type;
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isrc->isrc_nspc_type = INTR_IRQ_NSPC_NONE;
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isrc->isrc_trig = INTR_TRIGGER_CONFORM;
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isrc->isrc_pol = INTR_POLARITY_CONFORM;
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CPU_ZERO(&isrc->isrc_cpu);
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return (isrc);
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}
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/*
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* Free interrupt source.
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*/
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static void
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isrc_free(struct intr_irqsrc *isrc)
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{
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free(isrc, M_INTRNG);
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}
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void
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intr_irq_set_name(struct intr_irqsrc *isrc, const char *fmt, ...)
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{
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va_list ap;
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va_start(ap, fmt);
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vsnprintf(isrc->isrc_name, INTR_ISRC_NAMELEN, fmt, ap);
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va_end(ap);
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}
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/*
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* Alloc unique interrupt number (resource handle) for interrupt source.
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*
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* There could be various strategies how to allocate free interrupt number
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* (resource handle) for new interrupt source.
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*
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* 1. Handles are always allocated forward, so handles are not recycled
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* immediately. However, if only one free handle left which is reused
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* constantly...
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*/
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static int
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isrc_alloc_irq_locked(struct intr_irqsrc *isrc)
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{
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u_int maxirqs, irq;
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mtx_assert(&isrc_table_lock, MA_OWNED);
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maxirqs = nitems(irq_sources);
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if (irq_next_free >= maxirqs)
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return (ENOSPC);
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for (irq = irq_next_free; irq < maxirqs; irq++) {
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if (irq_sources[irq] == NULL)
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goto found;
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}
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for (irq = 0; irq < irq_next_free; irq++) {
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if (irq_sources[irq] == NULL)
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goto found;
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}
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irq_next_free = maxirqs;
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return (ENOSPC);
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found:
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isrc->isrc_irq = irq;
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irq_sources[irq] = isrc;
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intr_irq_set_name(isrc, "irq%u", irq);
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isrc_setup_counters(isrc);
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irq_next_free = irq + 1;
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if (irq_next_free >= maxirqs)
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irq_next_free = 0;
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return (0);
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}
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#ifdef notyet
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/*
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* Free unique interrupt number (resource handle) from interrupt source.
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*/
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static int
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isrc_free_irq(struct intr_irqsrc *isrc)
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{
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u_int maxirqs;
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mtx_assert(&isrc_table_lock, MA_NOTOWNED);
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maxirqs = nitems(irq_sources);
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if (isrc->isrc_irq >= maxirqs)
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return (EINVAL);
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mtx_lock(&isrc_table_lock);
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if (irq_sources[isrc->isrc_irq] != isrc) {
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mtx_unlock(&isrc_table_lock);
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return (EINVAL);
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}
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irq_sources[isrc->isrc_irq] = NULL;
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isrc->isrc_irq = IRQ_INVALID; /* just to be safe */
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mtx_unlock(&isrc_table_lock);
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return (0);
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}
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#endif
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/*
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* Lookup interrupt source by interrupt number (resource handle).
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*/
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static struct intr_irqsrc *
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isrc_lookup(u_int irq)
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{
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if (irq < nitems(irq_sources))
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return (irq_sources[irq]);
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return (NULL);
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}
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/*
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* Lookup interrupt source by namespace description.
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*/
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static struct intr_irqsrc *
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isrc_namespace_lookup(device_t dev, uint16_t type, uint16_t num)
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{
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u_int irq;
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struct intr_irqsrc *isrc;
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mtx_assert(&isrc_table_lock, MA_OWNED);
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for (irq = 0; irq < nitems(irq_sources); irq++) {
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isrc = irq_sources[irq];
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if (isrc != NULL && isrc->isrc_dev == dev &&
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isrc->isrc_nspc_type == type && isrc->isrc_nspc_num == num)
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return (isrc);
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}
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return (NULL);
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}
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|
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/*
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* Map interrupt source according to namespace into framework. If such mapping
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* does not exist, create it. Return unique interrupt number (resource handle)
|
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* associated with mapped interrupt source.
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*/
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u_int
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intr_namespace_map_irq(device_t dev, uint16_t type, uint16_t num)
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{
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struct intr_irqsrc *isrc, *new_isrc;
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int error;
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new_isrc = isrc_alloc(INTR_ISRCT_NAMESPACE, 0);
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|
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mtx_lock(&isrc_table_lock);
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isrc = isrc_namespace_lookup(dev, type, num);
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if (isrc != NULL) {
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mtx_unlock(&isrc_table_lock);
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isrc_free(new_isrc);
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return (isrc->isrc_irq); /* already mapped */
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}
|
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|
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error = isrc_alloc_irq_locked(new_isrc);
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if (error != 0) {
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mtx_unlock(&isrc_table_lock);
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isrc_free(new_isrc);
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return (IRQ_INVALID); /* no space left */
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}
|
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|
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new_isrc->isrc_dev = dev;
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new_isrc->isrc_nspc_type = type;
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new_isrc->isrc_nspc_num = num;
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mtx_unlock(&isrc_table_lock);
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return (new_isrc->isrc_irq);
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}
|
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|
|
#ifdef FDT
|
|
/*
|
|
* Lookup interrupt source by FDT description.
|
|
*/
|
|
static struct intr_irqsrc *
|
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isrc_fdt_lookup(intptr_t xref, pcell_t *cells, u_int ncells)
|
|
{
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u_int irq, cellsize;
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struct intr_irqsrc *isrc;
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mtx_assert(&isrc_table_lock, MA_OWNED);
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cellsize = ncells * sizeof(*cells);
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for (irq = 0; irq < nitems(irq_sources); irq++) {
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isrc = irq_sources[irq];
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if (isrc != NULL && isrc->isrc_type == INTR_ISRCT_FDT &&
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isrc->isrc_xref == xref && isrc->isrc_ncells == ncells &&
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memcmp(isrc->isrc_cells, cells, cellsize) == 0)
|
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return (isrc);
|
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}
|
|
return (NULL);
|
|
}
|
|
|
|
/*
|
|
* Map interrupt source according to FDT data into framework. If such mapping
|
|
* does not exist, create it. Return unique interrupt number (resource handle)
|
|
* associated with mapped interrupt source.
|
|
*/
|
|
u_int
|
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intr_fdt_map_irq(phandle_t node, pcell_t *cells, u_int ncells)
|
|
{
|
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struct intr_irqsrc *isrc, *new_isrc;
|
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u_int cellsize;
|
|
intptr_t xref;
|
|
int error;
|
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|
|
xref = (intptr_t)node; /* It's so simple for now. */
|
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|
|
cellsize = ncells * sizeof(*cells);
|
|
new_isrc = isrc_alloc(INTR_ISRCT_FDT, cellsize);
|
|
|
|
mtx_lock(&isrc_table_lock);
|
|
isrc = isrc_fdt_lookup(xref, cells, ncells);
|
|
if (isrc != NULL) {
|
|
mtx_unlock(&isrc_table_lock);
|
|
isrc_free(new_isrc);
|
|
return (isrc->isrc_irq); /* already mapped */
|
|
}
|
|
|
|
error = isrc_alloc_irq_locked(new_isrc);
|
|
if (error != 0) {
|
|
mtx_unlock(&isrc_table_lock);
|
|
isrc_free(new_isrc);
|
|
return (IRQ_INVALID); /* no space left */
|
|
}
|
|
|
|
new_isrc->isrc_xref = xref;
|
|
new_isrc->isrc_ncells = ncells;
|
|
memcpy(new_isrc->isrc_cells, cells, cellsize);
|
|
mtx_unlock(&isrc_table_lock);
|
|
|
|
return (new_isrc->isrc_irq);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Register interrupt source into interrupt controller.
|
|
*/
|
|
static int
|
|
isrc_register(struct intr_irqsrc *isrc)
|
|
{
|
|
struct intr_pic *pic;
|
|
boolean_t is_percpu;
|
|
int error;
|
|
|
|
if (isrc->isrc_flags & INTR_ISRCF_REGISTERED)
|
|
return (0);
|
|
|
|
if (isrc->isrc_dev == NULL) {
|
|
pic = pic_lookup(NULL, isrc->isrc_xref);
|
|
if (pic == NULL || pic->pic_dev == NULL)
|
|
return (ESRCH);
|
|
isrc->isrc_dev = pic->pic_dev;
|
|
}
|
|
|
|
error = PIC_REGISTER(isrc->isrc_dev, isrc, &is_percpu);
|
|
if (error != 0)
|
|
return (error);
|
|
|
|
mtx_lock(&isrc_table_lock);
|
|
isrc->isrc_flags |= INTR_ISRCF_REGISTERED;
|
|
if (is_percpu)
|
|
isrc->isrc_flags |= INTR_ISRCF_PERCPU;
|
|
isrc_update_name(isrc, NULL);
|
|
mtx_unlock(&isrc_table_lock);
|
|
return (0);
|
|
}
|
|
|
|
#ifdef INTR_SOLO
|
|
/*
|
|
* Setup filter into interrupt source.
|
|
*/
|
|
static int
|
|
iscr_setup_filter(struct intr_irqsrc *isrc, const char *name,
|
|
intr_irq_filter_t *filter, void *arg, void **cookiep)
|
|
{
|
|
|
|
if (filter == NULL)
|
|
return (EINVAL);
|
|
|
|
mtx_lock(&isrc_table_lock);
|
|
/*
|
|
* Make sure that we do not mix the two ways
|
|
* how we handle interrupt sources.
|
|
*/
|
|
if (isrc->isrc_filter != NULL || isrc->isrc_event != NULL) {
|
|
mtx_unlock(&isrc_table_lock);
|
|
return (EBUSY);
|
|
}
|
|
isrc->isrc_filter = filter;
|
|
isrc->isrc_arg = arg;
|
|
isrc_update_name(isrc, name);
|
|
mtx_unlock(&isrc_table_lock);
|
|
|
|
*cookiep = isrc;
|
|
return (0);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Interrupt source pre_ithread method for MI interrupt framework.
|
|
*/
|
|
static void
|
|
intr_isrc_pre_ithread(void *arg)
|
|
{
|
|
struct intr_irqsrc *isrc = arg;
|
|
|
|
PIC_PRE_ITHREAD(isrc->isrc_dev, isrc);
|
|
}
|
|
|
|
/*
|
|
* Interrupt source post_ithread method for MI interrupt framework.
|
|
*/
|
|
static void
|
|
intr_isrc_post_ithread(void *arg)
|
|
{
|
|
struct intr_irqsrc *isrc = arg;
|
|
|
|
PIC_POST_ITHREAD(isrc->isrc_dev, isrc);
|
|
}
|
|
|
|
/*
|
|
* Interrupt source post_filter method for MI interrupt framework.
|
|
*/
|
|
static void
|
|
intr_isrc_post_filter(void *arg)
|
|
{
|
|
struct intr_irqsrc *isrc = arg;
|
|
|
|
PIC_POST_FILTER(isrc->isrc_dev, isrc);
|
|
}
|
|
|
|
/*
|
|
* Interrupt source assign_cpu method for MI interrupt framework.
|
|
*/
|
|
static int
|
|
intr_isrc_assign_cpu(void *arg, int cpu)
|
|
{
|
|
#ifdef SMP
|
|
struct intr_irqsrc *isrc = arg;
|
|
int error;
|
|
|
|
if (isrc->isrc_dev != intr_irq_root_dev)
|
|
return (EINVAL);
|
|
|
|
mtx_lock(&isrc_table_lock);
|
|
if (cpu == NOCPU) {
|
|
CPU_ZERO(&isrc->isrc_cpu);
|
|
isrc->isrc_flags &= ~INTR_ISRCF_BOUND;
|
|
} else {
|
|
CPU_SETOF(cpu, &isrc->isrc_cpu);
|
|
isrc->isrc_flags |= INTR_ISRCF_BOUND;
|
|
}
|
|
|
|
/*
|
|
* In NOCPU case, it's up to PIC to either leave ISRC on same CPU or
|
|
* re-balance it to another CPU or enable it on more CPUs. However,
|
|
* PIC is expected to change isrc_cpu appropriately to keep us well
|
|
* informed if the call is successfull.
|
|
*/
|
|
if (irq_assign_cpu) {
|
|
error = PIC_BIND(isrc->isrc_dev, isrc);
|
|
if (error) {
|
|
CPU_ZERO(&isrc->isrc_cpu);
|
|
mtx_unlock(&isrc_table_lock);
|
|
return (error);
|
|
}
|
|
}
|
|
mtx_unlock(&isrc_table_lock);
|
|
return (0);
|
|
#else
|
|
return (EOPNOTSUPP);
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Create interrupt event for interrupt source.
|
|
*/
|
|
static int
|
|
isrc_event_create(struct intr_irqsrc *isrc)
|
|
{
|
|
struct intr_event *ie;
|
|
int error;
|
|
|
|
error = intr_event_create(&ie, isrc, 0, isrc->isrc_irq,
|
|
intr_isrc_pre_ithread, intr_isrc_post_ithread, intr_isrc_post_filter,
|
|
intr_isrc_assign_cpu, "%s:", isrc->isrc_name);
|
|
if (error)
|
|
return (error);
|
|
|
|
mtx_lock(&isrc_table_lock);
|
|
/*
|
|
* Make sure that we do not mix the two ways
|
|
* how we handle interrupt sources. Let contested event wins.
|
|
*/
|
|
#ifdef INTR_SOLO
|
|
if (isrc->isrc_filter != NULL || isrc->isrc_event != NULL) {
|
|
#else
|
|
if (isrc->isrc_event != NULL) {
|
|
#endif
|
|
mtx_unlock(&isrc_table_lock);
|
|
intr_event_destroy(ie);
|
|
return (isrc->isrc_event != NULL ? EBUSY : 0);
|
|
}
|
|
isrc->isrc_event = ie;
|
|
mtx_unlock(&isrc_table_lock);
|
|
|
|
return (0);
|
|
}
|
|
#ifdef notyet
|
|
/*
|
|
* Destroy interrupt event for interrupt source.
|
|
*/
|
|
static void
|
|
isrc_event_destroy(struct intr_irqsrc *isrc)
|
|
{
|
|
struct intr_event *ie;
|
|
|
|
mtx_lock(&isrc_table_lock);
|
|
ie = isrc->isrc_event;
|
|
isrc->isrc_event = NULL;
|
|
mtx_unlock(&isrc_table_lock);
|
|
|
|
if (ie != NULL)
|
|
intr_event_destroy(ie);
|
|
}
|
|
#endif
|
|
/*
|
|
* Add handler to interrupt source.
|
|
*/
|
|
static int
|
|
isrc_add_handler(struct intr_irqsrc *isrc, const char *name,
|
|
driver_filter_t filter, driver_intr_t handler, void *arg,
|
|
enum intr_type flags, void **cookiep)
|
|
{
|
|
int error;
|
|
|
|
if (isrc->isrc_event == NULL) {
|
|
error = isrc_event_create(isrc);
|
|
if (error)
|
|
return (error);
|
|
}
|
|
|
|
error = intr_event_add_handler(isrc->isrc_event, name, filter, handler,
|
|
arg, intr_priority(flags), flags, cookiep);
|
|
if (error == 0) {
|
|
mtx_lock(&isrc_table_lock);
|
|
intrcnt_updatename(isrc);
|
|
mtx_unlock(&isrc_table_lock);
|
|
}
|
|
|
|
return (error);
|
|
}
|
|
|
|
/*
|
|
* Lookup interrupt controller locked.
|
|
*/
|
|
static struct intr_pic *
|
|
pic_lookup_locked(device_t dev, intptr_t xref)
|
|
{
|
|
struct intr_pic *pic;
|
|
|
|
mtx_assert(&pic_list_lock, MA_OWNED);
|
|
|
|
SLIST_FOREACH(pic, &pic_list, pic_next) {
|
|
if (pic->pic_xref != xref)
|
|
continue;
|
|
if (pic->pic_xref != 0 || pic->pic_dev == dev)
|
|
return (pic);
|
|
}
|
|
return (NULL);
|
|
}
|
|
|
|
/*
|
|
* Lookup interrupt controller.
|
|
*/
|
|
static struct intr_pic *
|
|
pic_lookup(device_t dev, intptr_t xref)
|
|
{
|
|
struct intr_pic *pic;
|
|
|
|
mtx_lock(&pic_list_lock);
|
|
pic = pic_lookup_locked(dev, xref);
|
|
mtx_unlock(&pic_list_lock);
|
|
|
|
return (pic);
|
|
}
|
|
|
|
/*
|
|
* Create interrupt controller.
|
|
*/
|
|
static struct intr_pic *
|
|
pic_create(device_t dev, intptr_t xref)
|
|
{
|
|
struct intr_pic *pic;
|
|
|
|
mtx_lock(&pic_list_lock);
|
|
pic = pic_lookup_locked(dev, xref);
|
|
if (pic != NULL) {
|
|
mtx_unlock(&pic_list_lock);
|
|
return (pic);
|
|
}
|
|
pic = malloc(sizeof(*pic), M_INTRNG, M_NOWAIT | M_ZERO);
|
|
pic->pic_xref = xref;
|
|
pic->pic_dev = dev;
|
|
SLIST_INSERT_HEAD(&pic_list, pic, pic_next);
|
|
mtx_unlock(&pic_list_lock);
|
|
|
|
return (pic);
|
|
}
|
|
#ifdef notyet
|
|
/*
|
|
* Destroy interrupt controller.
|
|
*/
|
|
static void
|
|
pic_destroy(device_t dev, intptr_t xref)
|
|
{
|
|
struct intr_pic *pic;
|
|
|
|
mtx_lock(&pic_list_lock);
|
|
pic = pic_lookup_locked(dev, xref);
|
|
if (pic == NULL) {
|
|
mtx_unlock(&pic_list_lock);
|
|
return;
|
|
}
|
|
SLIST_REMOVE(&pic_list, pic, intr_pic, pic_next);
|
|
mtx_unlock(&pic_list_lock);
|
|
|
|
free(pic, M_INTRNG);
|
|
}
|
|
#endif
|
|
/*
|
|
* Register interrupt controller.
|
|
*/
|
|
int
|
|
intr_pic_register(device_t dev, intptr_t xref)
|
|
{
|
|
struct intr_pic *pic;
|
|
|
|
pic = pic_create(dev, xref);
|
|
if (pic == NULL)
|
|
return (ENOMEM);
|
|
if (pic->pic_dev != dev)
|
|
return (EINVAL); /* XXX it could be many things. */
|
|
|
|
debugf("PIC %p registered for %s <xref %x>\n", pic,
|
|
device_get_nameunit(dev), xref);
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Unregister interrupt controller.
|
|
*/
|
|
int
|
|
intr_pic_unregister(device_t dev, intptr_t xref)
|
|
{
|
|
|
|
panic("%s: not implemented", __func__);
|
|
}
|
|
|
|
/*
|
|
* Mark interrupt controller (itself) as a root one.
|
|
*
|
|
* Note that only an interrupt controller can really know its position
|
|
* in interrupt controller's tree. So root PIC must claim itself as a root.
|
|
*
|
|
* In FDT case, according to ePAPR approved version 1.1 from 08 April 2011,
|
|
* page 30:
|
|
* "The root of the interrupt tree is determined when traversal
|
|
* of the interrupt tree reaches an interrupt controller node without
|
|
* an interrupts property and thus no explicit interrupt parent."
|
|
*/
|
|
int
|
|
intr_pic_claim_root(device_t dev, intptr_t xref, intr_irq_filter_t *filter,
|
|
void *arg, u_int ipicount)
|
|
{
|
|
|
|
if (pic_lookup(dev, xref) == NULL) {
|
|
device_printf(dev, "not registered\n");
|
|
return (EINVAL);
|
|
}
|
|
if (filter == NULL) {
|
|
device_printf(dev, "filter missing\n");
|
|
return (EINVAL);
|
|
}
|
|
|
|
/*
|
|
* Only one interrupt controllers could be on the root for now.
|
|
* Note that we further suppose that there is not threaded interrupt
|
|
* routine (handler) on the root. See intr_irq_handler().
|
|
*/
|
|
if (intr_irq_root_dev != NULL) {
|
|
device_printf(dev, "another root already set\n");
|
|
return (EBUSY);
|
|
}
|
|
|
|
intr_irq_root_dev = dev;
|
|
irq_root_filter = filter;
|
|
irq_root_arg = arg;
|
|
irq_root_ipicount = ipicount;
|
|
|
|
debugf("irq root set to %s\n", device_get_nameunit(dev));
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
intr_irq_add_handler(device_t dev, driver_filter_t filt, driver_intr_t hand,
|
|
void *arg, u_int irq, int flags, void **cookiep)
|
|
{
|
|
const char *name;
|
|
struct intr_irqsrc *isrc;
|
|
int error;
|
|
|
|
name = device_get_nameunit(dev);
|
|
|
|
#ifdef INTR_SOLO
|
|
/*
|
|
* Standard handling is done thru MI interrupt framework. However,
|
|
* some interrupts could request solely own special handling. This
|
|
* non standard handling can be used for interrupt controllers without
|
|
* handler (filter only), so in case that interrupt controllers are
|
|
* chained, MI interrupt framework is called only in leaf controller.
|
|
*
|
|
* Note that root interrupt controller routine is served as well,
|
|
* however in intr_irq_handler(), i.e. main system dispatch routine.
|
|
*/
|
|
if (flags & INTR_SOLO && hand != NULL) {
|
|
debugf("irq %u cannot solo on %s\n", irq, name);
|
|
return (EINVAL);
|
|
}
|
|
#endif
|
|
|
|
isrc = isrc_lookup(irq);
|
|
if (isrc == NULL) {
|
|
debugf("irq %u without source on %s\n", irq, name);
|
|
return (EINVAL);
|
|
}
|
|
|
|
error = isrc_register(isrc);
|
|
if (error != 0) {
|
|
debugf("irq %u map error %d on %s\n", irq, error, name);
|
|
return (error);
|
|
}
|
|
|
|
#ifdef INTR_SOLO
|
|
if (flags & INTR_SOLO) {
|
|
error = iscr_setup_filter(isrc, name, (intr_irq_filter_t *)filt,
|
|
arg, cookiep);
|
|
debugf("irq %u setup filter error %d on %s\n", irq, error,
|
|
name);
|
|
} else
|
|
#endif
|
|
{
|
|
error = isrc_add_handler(isrc, name, filt, hand, arg, flags,
|
|
cookiep);
|
|
debugf("irq %u add handler error %d on %s\n", irq, error, name);
|
|
}
|
|
if (error != 0)
|
|
return (error);
|
|
|
|
mtx_lock(&isrc_table_lock);
|
|
isrc->isrc_handlers++;
|
|
if (isrc->isrc_handlers == 1) {
|
|
PIC_ENABLE_INTR(isrc->isrc_dev, isrc);
|
|
PIC_ENABLE_SOURCE(isrc->isrc_dev, isrc);
|
|
}
|
|
mtx_unlock(&isrc_table_lock);
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
intr_irq_remove_handler(device_t dev, u_int irq, void *cookie)
|
|
{
|
|
struct intr_irqsrc *isrc;
|
|
int error;
|
|
|
|
isrc = isrc_lookup(irq);
|
|
if (isrc == NULL || isrc->isrc_handlers == 0)
|
|
return (EINVAL);
|
|
#ifdef INTR_SOLO
|
|
if (isrc->isrc_filter != NULL) {
|
|
if (isrc != cookie)
|
|
return (EINVAL);
|
|
|
|
mtx_lock(&isrc_table_lock);
|
|
isrc->isrc_filter = NULL;
|
|
isrc->isrc_arg = NULL;
|
|
isrc->isrc_handlers = 0;
|
|
PIC_DISABLE_SOURCE(isrc->isrc_dev, isrc);
|
|
PIC_DISABLE_INTR(isrc->isrc_dev, isrc);
|
|
isrc_update_name(isrc, NULL);
|
|
mtx_unlock(&isrc_table_lock);
|
|
return (0);
|
|
}
|
|
#endif
|
|
if (isrc != intr_handler_source(cookie))
|
|
return (EINVAL);
|
|
|
|
error = intr_event_remove_handler(cookie);
|
|
if (error == 0) {
|
|
mtx_lock(&isrc_table_lock);
|
|
isrc->isrc_handlers--;
|
|
if (isrc->isrc_handlers == 0) {
|
|
PIC_DISABLE_SOURCE(isrc->isrc_dev, isrc);
|
|
PIC_DISABLE_INTR(isrc->isrc_dev, isrc);
|
|
}
|
|
intrcnt_updatename(isrc);
|
|
mtx_unlock(&isrc_table_lock);
|
|
}
|
|
return (error);
|
|
}
|
|
|
|
int
|
|
intr_irq_config(u_int irq, enum intr_trigger trig, enum intr_polarity pol)
|
|
{
|
|
struct intr_irqsrc *isrc;
|
|
|
|
isrc = isrc_lookup(irq);
|
|
if (isrc == NULL)
|
|
return (EINVAL);
|
|
|
|
if (isrc->isrc_handlers != 0)
|
|
return (EBUSY); /* interrrupt is enabled (active) */
|
|
|
|
/*
|
|
* Once an interrupt is enabled, we do not change its configuration.
|
|
* A controller PIC_ENABLE_INTR() method is called when an interrupt
|
|
* is going to be enabled. In this method, a controller should setup
|
|
* the interrupt according to saved configuration parameters.
|
|
*/
|
|
isrc->isrc_trig = trig;
|
|
isrc->isrc_pol = pol;
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
intr_irq_describe(u_int irq, void *cookie, const char *descr)
|
|
{
|
|
struct intr_irqsrc *isrc;
|
|
int error;
|
|
|
|
isrc = isrc_lookup(irq);
|
|
if (isrc == NULL || isrc->isrc_handlers == 0)
|
|
return (EINVAL);
|
|
#ifdef INTR_SOLO
|
|
if (isrc->isrc_filter != NULL) {
|
|
if (isrc != cookie)
|
|
return (EINVAL);
|
|
|
|
mtx_lock(&isrc_table_lock);
|
|
isrc_update_name(isrc, descr);
|
|
mtx_unlock(&isrc_table_lock);
|
|
return (0);
|
|
}
|
|
#endif
|
|
error = intr_event_describe_handler(isrc->isrc_event, cookie, descr);
|
|
if (error == 0) {
|
|
mtx_lock(&isrc_table_lock);
|
|
intrcnt_updatename(isrc);
|
|
mtx_unlock(&isrc_table_lock);
|
|
}
|
|
return (error);
|
|
}
|
|
|
|
#ifdef SMP
|
|
int
|
|
intr_irq_bind(u_int irq, int cpu)
|
|
{
|
|
struct intr_irqsrc *isrc;
|
|
|
|
isrc = isrc_lookup(irq);
|
|
if (isrc == NULL || isrc->isrc_handlers == 0)
|
|
return (EINVAL);
|
|
#ifdef INTR_SOLO
|
|
if (isrc->isrc_filter != NULL)
|
|
return (intr_isrc_assign_cpu(isrc, cpu));
|
|
#endif
|
|
return (intr_event_bind(isrc->isrc_event, cpu));
|
|
}
|
|
|
|
/*
|
|
* Return the CPU that the next interrupt source should use.
|
|
* For now just returns the next CPU according to round-robin.
|
|
*/
|
|
u_int
|
|
intr_irq_next_cpu(u_int last_cpu, cpuset_t *cpumask)
|
|
{
|
|
|
|
if (!irq_assign_cpu || mp_ncpus == 1)
|
|
return (PCPU_GET(cpuid));
|
|
|
|
do {
|
|
last_cpu++;
|
|
if (last_cpu > mp_maxid)
|
|
last_cpu = 0;
|
|
} while (!CPU_ISSET(last_cpu, cpumask));
|
|
return (last_cpu);
|
|
}
|
|
|
|
/*
|
|
* Distribute all the interrupt sources among the available
|
|
* CPUs once the AP's have been launched.
|
|
*/
|
|
static void
|
|
intr_irq_shuffle(void *arg __unused)
|
|
{
|
|
struct intr_irqsrc *isrc;
|
|
u_int i;
|
|
|
|
if (mp_ncpus == 1)
|
|
return;
|
|
|
|
mtx_lock(&isrc_table_lock);
|
|
irq_assign_cpu = TRUE;
|
|
for (i = 0; i < NIRQ; i++) {
|
|
isrc = irq_sources[i];
|
|
if (isrc == NULL || isrc->isrc_handlers == 0 ||
|
|
isrc->isrc_flags & INTR_ISRCF_PERCPU)
|
|
continue;
|
|
|
|
if (isrc->isrc_event != NULL &&
|
|
isrc->isrc_flags & INTR_ISRCF_BOUND &&
|
|
isrc->isrc_event->ie_cpu != CPU_FFS(&isrc->isrc_cpu) - 1)
|
|
panic("%s: CPU inconsistency", __func__);
|
|
|
|
if ((isrc->isrc_flags & INTR_ISRCF_BOUND) == 0)
|
|
CPU_ZERO(&isrc->isrc_cpu); /* start again */
|
|
|
|
/*
|
|
* We are in wicked position here if the following call fails
|
|
* for bound ISRC. The best thing we can do is to clear
|
|
* isrc_cpu so inconsistency with ie_cpu will be detectable.
|
|
*/
|
|
if (PIC_BIND(isrc->isrc_dev, isrc) != 0)
|
|
CPU_ZERO(&isrc->isrc_cpu);
|
|
}
|
|
mtx_unlock(&isrc_table_lock);
|
|
}
|
|
SYSINIT(intr_irq_shuffle, SI_SUB_SMP, SI_ORDER_SECOND, intr_irq_shuffle, NULL);
|
|
|
|
#else
|
|
u_int
|
|
intr_irq_next_cpu(u_int current_cpu, cpuset_t *cpumask)
|
|
{
|
|
|
|
return (PCPU_GET(cpuid));
|
|
}
|
|
#endif
|
|
|
|
void dosoftints(void);
|
|
void
|
|
dosoftints(void)
|
|
{
|
|
}
|
|
|
|
#ifdef SMP
|
|
/*
|
|
* Init interrupt controller on another CPU.
|
|
*/
|
|
void
|
|
intr_pic_init_secondary(void)
|
|
{
|
|
|
|
/*
|
|
* QQQ: Only root PIC is aware of other CPUs ???
|
|
*/
|
|
KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
|
|
|
|
//mtx_lock(&isrc_table_lock);
|
|
PIC_INIT_SECONDARY(intr_irq_root_dev);
|
|
//mtx_unlock(&isrc_table_lock);
|
|
}
|
|
#endif
|
|
|
|
#ifdef DDB
|
|
DB_SHOW_COMMAND(irqs, db_show_irqs)
|
|
{
|
|
u_int i, irqsum;
|
|
struct intr_irqsrc *isrc;
|
|
|
|
for (irqsum = 0, i = 0; i < NIRQ; i++) {
|
|
isrc = irq_sources[i];
|
|
if (isrc == NULL)
|
|
continue;
|
|
|
|
db_printf("irq%-3u <%s>: cpu %02lx%s cnt %lu\n", i,
|
|
isrc->isrc_name, isrc->isrc_cpu.__bits[0],
|
|
isrc->isrc_flags & INTR_ISRCF_BOUND ? " (bound)" : "",
|
|
isrc->isrc_count[0]);
|
|
irqsum += isrc->isrc_count[0];
|
|
}
|
|
db_printf("irq total %u\n", irqsum);
|
|
}
|
|
#endif
|