a4392a014c
finally have the f**king documentation!): 1) Changed all the numeric register offsets to symbolic ones (it should have been this way originally). 2) If 16 bit, disable the shared memory when not using it. Apparantly switching between 8/16bit mode makes the Ultra unhappy unless this is done (i.e. it trashes the bus).
963 lines
26 KiB
C
963 lines
26 KiB
C
/*
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* National Semiconductor DS8390 NIC register definitions
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*
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* $Id: if_edreg.h,v 1.13 1994/02/02 14:05:58 davidg Exp $
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*
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* Modification history
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*
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* Revision 2.2 1993/11/29 16:33:39 davidg
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* From Thomas Sandford <t.d.g.sandford@comp.brad.ac.uk>
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* Add support for the 8013W board type
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*
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* Revision 2.1 1993/11/22 10:52:33 davidg
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* patch to add support for SMC8216 (Elite-Ultra) boards
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* from Glen H. Lowe
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*
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* Revision 2.0 93/09/29 00:37:15 davidg
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* changed double buffering flag to multi buffering
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* made changes/additions for 3c503 multi-buffering
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* ...companion to Rev. 2.0 of 'ed' driver.
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*
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* Revision 1.1 93/06/23 03:01:07 davidg
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* Initial revision
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*
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*/
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/*
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* Page 0 register offsets
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*/
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#define ED_P0_CR 0x00 /* Command Register */
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#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */
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#define ED_P0_PSTART 0x01 /* Page Start register (write) */
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#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */
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#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */
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#define ED_P0_BNRY 0x03 /* Boundary Pointer */
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#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */
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#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */
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#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */
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#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */
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#define ED_P0_FIFO 0x06 /* FIFO register (read) */
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#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */
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#define ED_P0_ISR 0x07 /* Interrupt Status Register */
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#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */
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#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */
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#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */
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#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */
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#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */
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#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */
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#define ED_P0_RSR 0x0c /* Receive Status (read) */
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#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */
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#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */
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#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */
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#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */
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#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */
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#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */
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#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */
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/*
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* Page 1 register offsets
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*/
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#define ED_P1_CR 0x00 /* Command Register */
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#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */
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#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */
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#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */
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#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */
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#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */
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#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */
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#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */
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#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */
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#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */
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#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */
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#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */
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#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */
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#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */
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#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */
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#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */
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/*
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* Page 2 register offsets
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*/
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#define ED_P2_CR 0x00 /* Command Register */
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#define ED_P2_PSTART 0x01 /* Page Start (read) */
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#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */
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#define ED_P2_PSTOP 0x02 /* Page Stop (read) */
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#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */
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#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */
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#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */
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#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */
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#define ED_P2_ACU 0x06 /* Address Counter Upper */
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#define ED_P2_ACL 0x07 /* Address Counter Lower */
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#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */
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#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */
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#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */
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#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */
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/*
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* Command Register (CR) definitions
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*/
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/*
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* STP: SToP. Software reset command. Takes the controller offline. No
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* packets will be received or transmitted. Any reception or
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* transmission in progress will continue to completion before
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* entering reset state. To exit this state, the STP bit must
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* reset and the STA bit must be set. The software reset has
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* executed only when indicated by the RST bit in the ISR being
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* set.
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*/
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#define ED_CR_STP 0x01
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/*
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* STA: STArt. This bit is used to activate the NIC after either power-up,
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* or when the NIC has been put in reset mode by software command
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* or error.
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*/
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#define ED_CR_STA 0x02
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/*
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* TXP: Transmit Packet. This bit must be set to indicate transmission of
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* a packet. TXP is internally reset either after the transmission is
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* completed or aborted. This bit should be set only after the Transmit
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* Byte Count and Transmit Page Start register have been programmed.
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*/
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#define ED_CR_TXP 0x04
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/*
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* RD0, RD1, RD2: Remote DMA Command. These three bits control the operation
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* of the remote DMA channel. RD2 can be set to abort any remote DMA
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* command in progress. The Remote Byte Count registers should be cleared
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* when a remote DMA has been aborted. The Remote Start Addresses are not
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* restored to the starting address if the remote DMA is aborted.
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*
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* RD2 RD1 RD0 function
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* 0 0 0 not allowed
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* 0 0 1 remote read
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* 0 1 0 remote write
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* 0 1 1 send packet
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* 1 X X abort
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*/
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#define ED_CR_RD0 0x08
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#define ED_CR_RD1 0x10
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#define ED_CR_RD2 0x20
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/*
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* PS0, PS1: Page Select. The two bits select which register set or 'page' to
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* access.
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*
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* PS1 PS0 page
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* 0 0 0
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* 0 1 1
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* 1 0 2
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* 1 1 reserved
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*/
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#define ED_CR_PS0 0x40
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#define ED_CR_PS1 0x80
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/* bit encoded aliases */
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#define ED_CR_PAGE_0 0x00 /* (for consistency) */
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#define ED_CR_PAGE_1 0x40
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#define ED_CR_PAGE_2 0x80
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/*
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* Interrupt Status Register (ISR) definitions
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*/
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/*
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* PRX: Packet Received. Indicates packet received with no errors.
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*/
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#define ED_ISR_PRX 0x01
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/*
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* PTX: Packet Transmitted. Indicates packet transmitted with no errors.
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*/
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#define ED_ISR_PTX 0x02
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/*
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* RXE: Receive Error. Indicates that a packet was received with one or more
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* the following errors: CRC error, frame alignment error, FIFO overrun,
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* missed packet.
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*/
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#define ED_ISR_RXE 0x04
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/*
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* TXE: Transmission Error. Indicates that an attempt to transmit a packet
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* resulted in one or more of the following errors: excessive
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* collisions, FIFO underrun.
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*/
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#define ED_ISR_TXE 0x08
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/*
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* OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network
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* would exceed (has exceeded?) the boundry pointer, resulting in data
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* that was previously received and not yet read from the buffer to be
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* overwritten.
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*/
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#define ED_ISR_OVW 0x10
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/*
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* CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley
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* Counters has been set.
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*/
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#define ED_ISR_CNT 0x20
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/*
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* RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed.
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*/
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#define ED_ISR_RDC 0x40
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/*
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* RST: Reset status. Set when the NIC enters the reset state and cleared when a
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* Start Command is issued to the CR. This bit is also set when a receive
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* ring-buffer overrun (OverWrite) occurs and is cleared when one or more
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* packets have been removed from the ring. This is a read-only bit.
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*/
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#define ED_ISR_RST 0x80
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/*
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* Interrupt Mask Register (IMR) definitions
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*/
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/*
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* PRXE: Packet Received interrupt Enable. If set, a received packet will cause
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* an interrupt.
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*/
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#define ED_IMR_PRXE 0x01
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/*
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* PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when
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* a packet transmission completes.
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*/
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#define ED_IMR_PTXE 0x02
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/*
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* RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a
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* packet is received with an error.
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*/
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#define ED_IMR_RXEE 0x04
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/*
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* TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever
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* a transmission results in an error.
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*/
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#define ED_IMR_TXEE 0x08
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/*
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* OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever
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* the receive ring-buffer is overrun. i.e. when the boundry pointer is exceeded.
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*/
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#define ED_IMR_OVWE 0x10
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/*
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* CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever
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* the MSB of one or more of the Network Statistics counters has been set.
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*/
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#define ED_IMR_CNTE 0x20
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/*
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* RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated
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* when a remote DMA transfer has completed.
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*/
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#define ED_IMR_RDCE 0x40
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/*
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* bit 7 is unused/reserved
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*/
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/*
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* Data Configuration Register (DCR) definitions
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*/
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/*
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* WTS: Word Transfer Select. WTS establishes byte or word transfers for
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* both remote and local DMA transfers
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*/
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#define ED_DCR_WTS 0x01
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/*
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* BOS: Byte Order Select. BOS sets the byte order for the host.
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* Should be 0 for 80x86, and 1 for 68000 series processors
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*/
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#define ED_DCR_BOS 0x02
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/*
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* LAS: Long Address Select. When LAS is 1, the contents of the remote
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* DMA registers RSAR0 and RSAR1 are used to provide A16-A31
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*/
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#define ED_DCR_LAS 0x04
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/*
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* LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2
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* of the TCR must also be programmed for loopback operation.
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* When 1, normal operation is selected.
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*/
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#define ED_DCR_LS 0x08
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/*
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* AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer
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* under program control. When 1, remote DMA is automatically initiated
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* and the boundry pointer is automatically updated
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*/
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#define ED_DCR_AR 0x10
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/*
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* FT0, FT1: Fifo Threshold select.
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* FT1 FT0 Word-width Byte-width
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* 0 0 1 word 2 bytes
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* 0 1 2 words 4 bytes
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* 1 0 4 words 8 bytes
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* 1 1 8 words 12 bytes
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*
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* During transmission, the FIFO threshold indicates the number of bytes
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* or words that the FIFO has filled from the local DMA before BREQ is
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* asserted. The transmission threshold is 16 bytes minus the receiver
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* threshold.
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*/
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#define ED_DCR_FT0 0x20
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#define ED_DCR_FT1 0x40
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/*
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* bit 7 (0x80) is unused/reserved
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*/
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/*
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* Transmit Configuration Register (TCR) definitions
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*/
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/*
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* CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC
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* is not appended by the transmitter.
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*/
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#define ED_TCR_CRC 0x01
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/*
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* LB0, LB1: Loopback control. These two bits set the type of loopback that is
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* to be performed.
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*
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* LB1 LB0 mode
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* 0 0 0 - normal operation (DCR_LS = 0)
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* 0 1 1 - internal loopback (DCR_LS = 0)
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* 1 0 2 - external loopback (DCR_LS = 1)
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* 1 1 3 - external loopback (DCR_LS = 0)
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*/
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#define ED_TCR_LB0 0x02
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#define ED_TCR_LB1 0x04
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/*
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* ATD: Auto Transmit Disable. Clear for normal operation. When set, allows
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* another station to disable the NIC's transmitter by transmitting to
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* a multicast address hashing to bit 62. Reception of a multicast address
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* hashing to bit 63 enables the transmitter.
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*/
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#define ED_TCR_ATD 0x08
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/*
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* OFST: Collision Offset enable. This bit when set modifies the backoff
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* algorithm to allow prioritization of nodes.
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*/
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#define ED_TCR_OFST 0x10
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/*
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* bits 5, 6, and 7 are unused/reserved
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*/
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/*
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* Transmit Status Register (TSR) definitions
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*/
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/*
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* PTX: Packet Transmitted. Indicates successful transmission of packet.
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*/
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#define ED_TSR_PTX 0x01
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/*
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* bit 1 (0x02) is unused/reserved
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*/
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/*
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* COL: Transmit Collided. Indicates that the transmission collided at least
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* once with another station on the network.
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*/
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#define ED_TSR_COL 0x04
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/*
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* ABT: Transmit aborted. Indicates that the transmission was aborted due to
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* excessive collisions.
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*/
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#define ED_TSR_ABT 0x08
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/*
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* CRS: Carrier Sense Lost. Indicates that carrier was lost during the
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* transmission of the packet. (Transmission is not aborted because
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* of a loss of carrier)
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*/
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#define ED_TSR_CRS 0x10
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/*
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* FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/
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* transmission memory before the FIFO emptied. Transmission of the
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* packet was aborted.
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*/
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#define ED_TSR_FU 0x20
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/*
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* CDH: CD Heartbeat. Indicates that the collision detection circuitry
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* isn't working correctly during a collision heartbeat test.
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*/
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#define ED_TSR_CDH 0x40
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/*
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* OWC: Out of Window Collision: Indicates that a collision occurred after
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* a slot time (51.2us). The transmission is rescheduled just as in
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* normal collisions.
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*/
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#define ED_TSR_OWC 0x80
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/*
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* Receiver Configuration Register (RCR) definitions
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*/
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/*
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* SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1,
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* packets with CRC and frame errors are not discarded.
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*/
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#define ED_RCR_SEP 0x01
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/*
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* AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded.
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* If set to 1, packets with less than 64 byte are not discarded.
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*/
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#define ED_RCR_AR 0x02
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/*
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* AB: Accept Broadcast. If set, packets sent to the broadcast address will be
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* accepted.
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*/
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#define ED_RCR_AB 0x04
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/*
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* AM: Accept Multicast. If set, packets sent to a multicast address are checked
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* for a match in the hashing array. If clear, multicast packets are ignored.
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*/
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#define ED_RCR_AM 0x08
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/*
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* PRO: Promiscuous Physical. If set, all packets with a physical addresses are
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* accepted. If clear, a physical destination address must match this
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* station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM
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* must also be set. In addition, the multicast hashing array must be set
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* to all 1's so that all multicast addresses are accepted.
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*/
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#define ED_RCR_PRO 0x10
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/*
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* MON: Monitor Mode. If set, packets will be checked for good CRC and framing,
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* but are not stored in the ring-buffer. If clear, packets are stored (normal
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* operation).
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*/
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#define ED_RCR_MON 0x20
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/*
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* bits 6 and 7 are unused/reserved.
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*/
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/*
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* Receiver Status Register (RSR) definitions
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*/
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/*
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* PRX: Packet Received without error.
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*/
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#define ED_RSR_PRX 0x01
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/*
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* CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame
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* alignment errors.
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*/
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#define ED_RSR_CRC 0x02
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/*
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* FAE: Frame Alignment Error. Indicates that the incoming packet did not end on
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* a byte boundry and the CRC did not match at the last byte boundry.
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*/
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#define ED_RSR_FAE 0x04
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/*
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* FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA)
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* causing it to overrun. Reception of the packet is aborted.
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*/
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#define ED_RSR_FO 0x08
|
|
|
|
/*
|
|
* MPA: Missed Packet. Indicates that the received packet couldn't be stored in
|
|
* the ring-buffer because of insufficient buffer space (exceeding the
|
|
* boundry pointer), or because the transfer to the ring-buffer was inhibited
|
|
* by RCR_MON - monitor mode.
|
|
*/
|
|
#define ED_RSR_MPA 0x10
|
|
|
|
/*
|
|
* PHY: Physical address. If 0, the packet received was sent to a physical address.
|
|
* If 1, the packet was accepted because of a multicast/broadcast address
|
|
* match.
|
|
*/
|
|
#define ED_RSR_PHY 0x20
|
|
|
|
/*
|
|
* DIS: Receiver Disabled. Set to indicate that the receiver has enetered monitor
|
|
* mode. Cleared when the receiver exits monitor mode.
|
|
*/
|
|
#define ED_RSR_DIS 0x40
|
|
|
|
/*
|
|
* DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs
|
|
* are active, and the transceiver has set the CD line as a result of the
|
|
* jabber.
|
|
*/
|
|
#define ED_RSR_DFR 0x80
|
|
|
|
/*
|
|
* receive ring discriptor
|
|
*
|
|
* The National Semiconductor DS8390 Network interface controller uses
|
|
* the following receive ring headers. The way this works is that the
|
|
* memory on the interface card is chopped up into 256 bytes blocks.
|
|
* A contiguous portion of those blocks are marked for receive packets
|
|
* by setting start and end block #'s in the NIC. For each packet that
|
|
* is put into the receive ring, one of these headers (4 bytes each) is
|
|
* tacked onto the front.
|
|
*/
|
|
struct ed_ring {
|
|
struct edr_status { /* received packet status */
|
|
u_char rs_prx:1, /* packet received intack */
|
|
rs_crc:1, /* crc error */
|
|
rs_fae:1, /* frame alignment error */
|
|
rs_fo:1, /* fifo overrun */
|
|
rs_mpa:1, /* packet received intack */
|
|
rs_phy:1, /* packet received intack */
|
|
rs_dis:1, /* packet received intack */
|
|
rs_dfr:1; /* packet received intack */
|
|
} ed_rcv_status; /* received packet status */
|
|
u_char next_packet; /* pointer to next packet */
|
|
u_short count; /* bytes in packet (length + 4) */
|
|
};
|
|
|
|
/*
|
|
* Common constants
|
|
*/
|
|
#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */
|
|
#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */
|
|
|
|
/*
|
|
* Vendor types
|
|
*/
|
|
#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */
|
|
#define ED_VENDOR_3COM 0x01 /* 3Com */
|
|
#define ED_VENDOR_NOVELL 0x02 /* Novell */
|
|
|
|
/*
|
|
* Compile-time config flags
|
|
*/
|
|
/*
|
|
* this sets the default for enabling/disablng the tranceiver
|
|
*/
|
|
#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001
|
|
|
|
/*
|
|
* This forces the board to be used in 8/16bit mode even if it
|
|
* autoconfigs differently
|
|
*/
|
|
#define ED_FLAGS_FORCE_8BIT_MODE 0x0002
|
|
#define ED_FLAGS_FORCE_16BIT_MODE 0x0004
|
|
|
|
/*
|
|
* This disables the use of double transmit buffers.
|
|
*/
|
|
#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008
|
|
|
|
/*
|
|
* This forces all operations with the NIC memory to use Programmed
|
|
* I/O (i.e. not via shared memory)
|
|
*/
|
|
#define ED_FLAGS_FORCE_PIO 0x0010
|
|
|
|
/*
|
|
* Definitions for Western digital/SMC WD80x3 series ASIC
|
|
*/
|
|
/*
|
|
* Memory Select Register (MSR)
|
|
*/
|
|
#define ED_WD_MSR 0
|
|
|
|
/* next three definitions for Toshiba */
|
|
#define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */
|
|
#define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */
|
|
#define ED_WD_MSR_LEN 0x20 /* data bus width, 0 = 16 bits,
|
|
1 = 8 bits (R/W) */
|
|
#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */
|
|
#define ED_WD_MSR_MENB 0x40 /* Memory enable */
|
|
#define ED_WD_MSR_RST 0x80 /* Reset board */
|
|
|
|
/*
|
|
* Interface Configuration Register (ICR)
|
|
*/
|
|
#define ED_WD_ICR 1
|
|
|
|
#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */
|
|
#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */
|
|
#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */
|
|
#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */
|
|
#define ED_WD_ICR_RLA 0x10 /* recall LAN address */
|
|
#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */
|
|
#define ED_WD_ICR_RIO 0x40 /* recall i/o address */
|
|
#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */
|
|
#ifdef TOSH_ETHER
|
|
#define ED_WD_ICR_MEM 0xe0 /* shared mem address A15-A13 (R/W) */
|
|
#define ED_WD_ICR_MSZ1 0x0f /* memory size, 0x08 = 64K, 0x04 = 32K,
|
|
0x02 = 16K, 0x01 = 8K */
|
|
/* 64K can only be used if mem address
|
|
above 1Mb */
|
|
/* IAR holds address A23-A16 (R/W) */
|
|
#endif
|
|
|
|
/*
|
|
* IO Address Register (IAR)
|
|
*/
|
|
#define ED_WD_IAR 2
|
|
|
|
/*
|
|
* EEROM Address Register
|
|
*/
|
|
#define ED_WD_EAR 3
|
|
|
|
/*
|
|
* Interrupt Request Register (IRR)
|
|
*/
|
|
#define ED_WD_IRR 4
|
|
|
|
#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */
|
|
#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */
|
|
#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */
|
|
#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */
|
|
#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */
|
|
|
|
/*
|
|
* The three bits of the encoded IRQ are decoded as follows:
|
|
*
|
|
* IR2 IR1 IR0 IRQ
|
|
* 0 0 0 2/9
|
|
* 0 0 1 3
|
|
* 0 1 0 5
|
|
* 0 1 1 7
|
|
* 1 0 0 10
|
|
* 1 0 1 11
|
|
* 1 1 0 15
|
|
* 1 1 1 4
|
|
*/
|
|
#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */
|
|
#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */
|
|
#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */
|
|
|
|
/*
|
|
* LA Address Register (LAAR)
|
|
*/
|
|
#define ED_WD_LAAR 5
|
|
|
|
#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */
|
|
#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */
|
|
#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */
|
|
#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */
|
|
|
|
/* i/o base offset to station address/card-ID PROM */
|
|
#define ED_WD_PROM 8
|
|
|
|
/*
|
|
* 83C790 specific registers
|
|
*/
|
|
/*
|
|
* Hardware Support Register (HWR) ('790)
|
|
*/
|
|
#define ED_WD790_HWR 4
|
|
|
|
#define WD_WD790_HWR_NUKE 0x10 /* hardware reset */
|
|
#define ED_WD790_HWR_LPRM 0x40 /* LAN PROM select */
|
|
#define ED_WD790_HWR_SWH 0x80 /* switch register set */
|
|
|
|
/*
|
|
* ICR790 Interrupt Control Register for the 83C790
|
|
*/
|
|
#define ED_WD790_ICR 6
|
|
|
|
#define ED_WD790_ICR_EIL 0x01 /* enable interrupts */
|
|
|
|
/*
|
|
* General Control Register (GCR)
|
|
* Enabled with SWH bit=1 in HWR register
|
|
*/
|
|
#define ED_WD790_GCR 0x0d
|
|
|
|
#define ED_WD790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */
|
|
#define ED_WD790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */
|
|
#define ED_WD790_GCR_ZWSEN 0x20 /* zero wait state enable */
|
|
#define ED_WD790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */
|
|
/*
|
|
* The three bits of the encoded IRQ are decoded as follows:
|
|
*
|
|
* IR2 IR1 IR0 IRQ
|
|
* 0 0 0 none
|
|
* 0 0 1 9
|
|
* 0 1 0 3
|
|
* 0 1 1 5
|
|
* 1 0 0 7
|
|
* 1 0 1 10
|
|
* 1 1 0 11
|
|
* 1 1 1 15
|
|
*/
|
|
|
|
/* i/o base offset to CARD ID */
|
|
#define ED_WD_CARD_ID ED_WD_PROM+6
|
|
|
|
/* Board type codes in card ID */
|
|
#define ED_TYPE_WD8003S 0x02
|
|
#define ED_TYPE_WD8003E 0x03
|
|
#define ED_TYPE_WD8013EBT 0x05
|
|
#define ED_TYPE_TOSHIBA1 0x11 /* named PCETA1 */
|
|
#define ED_TYPE_TOSHIBA2 0x12 /* named PCETA2 */
|
|
#define ED_TYPE_TOSHIBA3 0x13 /* named PCETB */
|
|
#define ED_TYPE_TOSHIBA4 0x14 /* named PCETC */
|
|
#define ED_TYPE_WD8003W 0x24
|
|
#define ED_TYPE_WD8003EB 0x25
|
|
#define ED_TYPE_WD8013W 0x26
|
|
#define ED_TYPE_WD8013EP 0x27
|
|
#define ED_TYPE_WD8013WC 0x28
|
|
#define ED_TYPE_WD8013EPC 0x29
|
|
#define ED_TYPE_SMC8216T 0x2a
|
|
#define ED_TYPE_SMC8216C 0x2b
|
|
#define ED_TYPE_WD8013EBP 0x2c
|
|
|
|
/* Bit definitions in card ID */
|
|
#define ED_WD_REV_MASK 0x1f /* Revision mask */
|
|
#define ED_WD_SOFTCONFIG 0x20 /* Soft config */
|
|
#define ED_WD_LARGERAM 0x40 /* Large RAM */
|
|
#define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */
|
|
|
|
/*
|
|
* Checksum total. All 8 bytes in station address PROM will add up to this
|
|
*/
|
|
#ifdef TOSH_ETHER
|
|
#define ED_WD_ROM_CHECKSUM_TOTAL 0xA5
|
|
#else
|
|
#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF
|
|
#endif
|
|
|
|
#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */
|
|
#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */
|
|
#define ED_WD_IO_PORTS 32 /* # of i/o addresses used */
|
|
|
|
#define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */
|
|
|
|
/*
|
|
* Definitions for 3Com 3c503
|
|
*/
|
|
#define ED_3COM_NIC_OFFSET 0
|
|
#define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */
|
|
|
|
/*
|
|
* XXX - The I/O address range is fragmented in the 3c503; this is the
|
|
* number of regs at iobase.
|
|
*/
|
|
#define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */
|
|
|
|
/* tx memory starts in second bank on 8bit cards */
|
|
#define ED_3COM_TX_PAGE_OFFSET_8BIT 0x20
|
|
|
|
/* tx memory starts in first bank on 16bit cards */
|
|
#define ED_3COM_TX_PAGE_OFFSET_16BIT 0x0
|
|
|
|
/* ...and rx memory starts in second bank */
|
|
#define ED_3COM_RX_PAGE_OFFSET_16BIT 0x20
|
|
|
|
|
|
/*
|
|
* Page Start Register. Must match PSTART in NIC
|
|
*/
|
|
#define ED_3COM_PSTR 0
|
|
|
|
/*
|
|
* Page Stop Register. Must match PSTOP in NIC
|
|
*/
|
|
#define ED_3COM_PSPR 1
|
|
|
|
/*
|
|
* Drq Timer Register. Determines number of bytes to be transfered during
|
|
* a DMA burst.
|
|
*/
|
|
#define ED_3COM_DQTR 2
|
|
|
|
/*
|
|
* Base Configuration Register. Read-only register which contains the
|
|
* board-configured I/O base address of the adapter. Bit encoded.
|
|
*/
|
|
#define ED_3COM_BCFR 3
|
|
|
|
#define ED_3COM_BCFR_2E0 0x01
|
|
#define ED_3COM_BCFR_2A0 0x02
|
|
#define ED_3COM_BCFR_280 0x04
|
|
#define ED_3COM_BCFR_250 0x08
|
|
#define ED_3COM_BCFR_350 0x10
|
|
#define ED_3COM_BCFR_330 0x20
|
|
#define ED_3COM_BCFR_310 0x40
|
|
#define ED_3COM_BCFR_300 0x80
|
|
|
|
/*
|
|
* EPROM Configuration Register. Read-only register which contains the
|
|
* board-configured memory base address. Bit encoded.
|
|
*/
|
|
#define ED_3COM_PCFR 4
|
|
|
|
#define ED_3COM_PCFR_C8000 0x10
|
|
#define ED_3COM_PCFR_CC000 0x20
|
|
#define ED_3COM_PCFR_D8000 0x40
|
|
#define ED_3COM_PCFR_DC000 0x80
|
|
|
|
/*
|
|
* GA Configuration Register. Gate-Array Configuration Register.
|
|
*/
|
|
#define ED_3COM_GACFR 5
|
|
|
|
/*
|
|
* mbs2 mbs1 mbs0 start address
|
|
* 0 0 0 0x0000
|
|
* 0 0 1 0x2000
|
|
* 0 1 0 0x4000
|
|
* 0 1 1 0x6000
|
|
*
|
|
* Note that with adapters with only 8K, the setting for 0x2000 must
|
|
* always be used.
|
|
*/
|
|
#define ED_3COM_GACFR_MBS0 0x01
|
|
#define ED_3COM_GACFR_MBS1 0x02
|
|
#define ED_3COM_GACFR_MBS2 0x04
|
|
|
|
#define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */
|
|
#define ED_3COM_GACFR_TEST 0x10 /* for GA testing */
|
|
#define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */
|
|
#define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */
|
|
#define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */
|
|
|
|
/*
|
|
* Control Register. Miscellaneous control functions.
|
|
*/
|
|
#define ED_3COM_CR 6
|
|
|
|
#define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */
|
|
#define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */
|
|
#define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */
|
|
#define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */
|
|
#define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */
|
|
#define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */
|
|
#define ED_3COM_CR_DDIR 0x40 /* DMA direction select */
|
|
#define ED_3COM_CR_START 0x80 /* Start DMA controller */
|
|
|
|
/*
|
|
* Status Register. Miscellaneous status information.
|
|
*/
|
|
#define ED_3COM_STREG 7
|
|
|
|
#define ED_3COM_STREG_REV 0x07 /* GA revision */
|
|
#define ED_3COM_STREG_DIP 0x08 /* DMA in progress */
|
|
#define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */
|
|
#define ED_3COM_STREG_OFLW 0x20 /* Overflow */
|
|
#define ED_3COM_STREG_UFLW 0x40 /* Underflow */
|
|
#define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */
|
|
|
|
/*
|
|
* Interrupt/DMA Configuration Register
|
|
*/
|
|
#define ED_3COM_IDCFR 8
|
|
|
|
#define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */
|
|
#define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */
|
|
#define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */
|
|
#define ED_3COM_IDCFR_UNUSED 0x08 /* not used */
|
|
#define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */
|
|
#define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */
|
|
#define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */
|
|
#define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */
|
|
|
|
/*
|
|
* DMA Address Register MSB
|
|
*/
|
|
#define ED_3COM_DAMSB 9
|
|
|
|
/*
|
|
* DMA Address Register LSB
|
|
*/
|
|
#define ED_3COM_DALSB 0x0a
|
|
|
|
/*
|
|
* Vector Pointer Register 2
|
|
*/
|
|
#define ED_3COM_VPTR2 0x0b
|
|
|
|
/*
|
|
* Vector Pointer Register 1
|
|
*/
|
|
#define ED_3COM_VPTR1 0x0c
|
|
|
|
/*
|
|
* Vector Pointer Register 0
|
|
*/
|
|
#define ED_3COM_VPTR0 0x0d
|
|
|
|
/*
|
|
* Register File Access MSB
|
|
*/
|
|
#define ED_3COM_RFMSB 0x0e
|
|
|
|
/*
|
|
* Register File Access LSB
|
|
*/
|
|
#define ED_3COM_RFLSB 0x0f
|
|
|
|
/*
|
|
* Definitions for Novell NE1000/2000 boards
|
|
*/
|
|
|
|
/*
|
|
* Board type codes
|
|
*/
|
|
#define ED_TYPE_NE1000 0x01
|
|
#define ED_TYPE_NE2000 0x02
|
|
|
|
/*
|
|
* Register offsets/total
|
|
*/
|
|
#define ED_NOVELL_NIC_OFFSET 0x00
|
|
#define ED_NOVELL_ASIC_OFFSET 0x10
|
|
#define ED_NOVELL_IO_PORTS 32
|
|
|
|
/*
|
|
* Remote DMA data register; for reading or writing to the NIC mem
|
|
* via programmed I/O (offset from ASIC base)
|
|
*/
|
|
#define ED_NOVELL_DATA 0x00
|
|
|
|
/*
|
|
* Reset register; reading from this register causes a board reset
|
|
*/
|
|
#define ED_NOVELL_RESET 0x0f
|