d09031f528
USB support This revision adds USB (EHCI/OHCI/OTG, depending on SoC type) support for various Ralink/Mediatek SoCs. Currently USB is not supported on MT7621, this will be a future addition. A USB PHY driver is also included, so that we can properly initialize the USB PHY (e.g., clocks, resets, registers where needed), before attempting to initialize EHCI/OHCI/OTG functionality. Approved by: adrian (mentor) Sponsored by: Smartcom - Bulgaria AD Differential Revision: https://reviews.freebsd.org/D5841
67 lines
2.3 KiB
C
67 lines
2.3 KiB
C
/*-
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* Copyright (c) 2016 Stanislav Galabov.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MTK_USB_PHY_H_
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#define _MTK_USB_PHY_H_
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#define MT7621_FM_FEG_BASE 0x0100
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#define MT7621_U2_BASE 0x0800
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#define MT7621_U2_BASE_P1 0x1000
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#define MT7621_SR_COEF 28
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#define MT7628_FM_FEG_BASE 0x0f00
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#define MT7628_U2_BASE 0x0800
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#define MT7628_SR_COEF 32
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#define U2_PHY_AC0 0x00
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#define U2_PHY_AC1 0x04
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#define U2_PHY_AC2 0x08
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#define U2_PHY_ACR0 0x10
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#define SRCAL_EN (1<<23)
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#define SRCTRL_MSK 0x7
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#define SRCTRL_OFF 16
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#define SRCTRL (SRCTRL_MSK<<SRCTRL_OFF)
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#define U2_PHY_ACR1 0x14
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#define U2_PHY_ACR2 0x18
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#define U2_PHY_ACR3 0x1C
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#define U2_PHY_DCR0 0x60
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#define U2_PHY_DCR1 0x64
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#define U2_PHY_DTM0 0x68
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#define U2_PHY_DTM1 0x6C
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#define U2_PHY_FMCR0 0x00
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#define CYCLECNT (0xffffff)
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#define FDET_EN (1<<24)
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#define U2_PHY_FMCR1 0x04
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#define FRCK_EN (1<<8)
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#define U2_PHY_FMCR2 0x08
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#define U2_PHY_FMMONR0 0x0C
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#define U2_PHY_FMMONR1 0x10
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#endif /* _MTK_USB_PHY_H_ */
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