512 lines
20 KiB
Plaintext
512 lines
20 KiB
Plaintext
<!-- $Id: dma.sgml,v 1.2 1995/11/20 01:10:12 jfieber Exp $ -->
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<!-- The FreeBSD Documentation Project -->
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<!--
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<!DOCTYPE linuxdoc PUBLIC "-//FreeBSD//DTD linuxdoc//EN" [
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<!ENTITY % authors SYSTEM "authors.sgml">
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%authors;
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]>
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-->
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<sect><heading>DMA: What it is and how it works<label id="dma"></heading>
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<p><em>Copyright © 1995 &a.uhclem;, All Rights Reserved.<newline>
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18 October 1995.</em>
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<!-- Version 1(2) -->
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Direct Memory Access (DMA) is a method of allowing data to
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be moved from one location to another in a computer without
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intervention from the central processor (CPU).
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The way that the DMA function is implemented varies between
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computer architectures, so this discussion will limit
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itself to the implementation and workings of the DMA
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subsystem on the IBM Personal Computer (PC), the IBM PC/AT
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and all of its successors and clones.
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The PC DMA subsystem is based on the Intel 8237 DMA
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controller. The 8237 contains four DMA channels that can
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be programmed independently and any of the channels may be
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active at any moment. These channels are numbered 0, 1, 2
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and 3. Starting with the PC/AT, IBM added a second 8237
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chip, and numbered those channels 4, 5, 6 and 7.
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The original DMA controller (0, 1, 2 and 3) moves one byte
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in each transfer. The second DMA controller (4, 5, 6, and
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7) moves 16-bits in each transfer. The two controllers are
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identical and the difference in transfer size is caused by
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the way the second controller is wired into the system.
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The 8237 has two electrical signals for each channel, named
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DRQ and -DACK. There are additional signals with the
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names HRQ (Hold Request), HLDA (Hold Acknowledge), -EOP
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(End of Process), and the bus control signals -MEMR (Memory
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Read), -MEMW (Memory Write), -IOR (I/O Read), and -IOW (I/O
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Write).
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The 8237 DMA is known as a ``fly-by'' DMA controller. This
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means that the data being moved from one location to
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another does not pass through the DMA chip and is not
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stored in the DMA chip. Subsequently, the DMA can only
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transfer data between an I/O port and a memory address, but
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not between two I/O ports or two memory locations.
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<quote><em>Note:</em> The 8237 does allow two channels to
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be connected together to allow memory-to-memory DMA
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operations in a non-``fly-by'' mode, but nobody in the PC
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industry uses this scarce resource this way since it is
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faster to move data between memory locations using the
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CPU.</quote>
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In the PC architecture, each DMA channel is normally
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activated only when the hardware that uses that DMA
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requests a transfer by asserting the DRQ line for that
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channel.
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<sect1><heading>A Sample DMA transfer</heading>
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<p>Here is an example of the steps that occur to cause a
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DMA transfer. In this example, the floppy disk
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controller (FDC) has just read a byte from a diskette and
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wants the DMA to place it in memory at location
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0x00123456. The process begins by the FDC asserting the
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DRQ2 signal to alert the DMA controller.
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The DMA controller will note that the DRQ2 signal is asserted.
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The DMA controller will then make sure that DMA channel 2
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has been programmed and is enabled. The DMA controller
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also makes sure that none of the other DMA channels are active
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or have a higher priority. Once these checks are
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complete, the DMA asks the CPU to release the bus so that
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the DMA may use the bus. The DMA requests the bus by
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asserting the HRQ signal which goes to the CPU.
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The CPU detects the HRQ signal, and will complete
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executing the current instruction. Once the processor
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has reached a state where it can release the bus, it
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will. Now all of the signals normally generated by the
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CPU (-MEMR, -MEMW, -IOR, -IOW and a few others) are
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placed in a tri-stated condition (neither high or low)
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and then the CPU asserts the HLDA signal which tells the
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DMA controller that it is now in charge of the bus.
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Depending on the processor, the CPU may be able to
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execute a few additional instructions now that it no
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longer has the bus, but the CPU will eventually have to
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wait when it reaches an instruction that must read
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something from memory that is not in the internal
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processor cache or pipeline.
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Now that the DMA ``is in charge'', the DMA activates its
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-MEMR, -MEMW, -IOR, -IOW output signals, and the address
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outputs from the DMA are set to 0x3456, which will be
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used to direct the byte that is about to transferred to a
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specific memory location.
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The DMA will then let the device that requested the DMA
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transfer know that the transfer is commencing. This is
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done by asserting the -DACK signal, or in the case of the
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floppy disk controller, -DACK2 is asserted.
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The floppy disk controller is now responsible for placing
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the byte to be transferred on the bus Data lines. Unless
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the floppy controller needs more time to get the data
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byte on the bus (and if the peripheral needs more time it
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alerts the DMA via the READY signal), the DMA will wait
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one DMA clock, and then de-assert the -MEMW and -IOR
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signals so that the memory will latch and store the byte
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that was on the bus, and the FDC will know that the byte
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has been transferred.
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Since the DMA cycle only transfers a single byte at a
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time, the FDC now drops the DRQ2 signal, so that the DMA
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knows it is no longer needed. The DMA will de-assert the
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-DACK2 signal, so that the FDC knows it must stop placing
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data on the bus.
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The DMA will now check to see if any of the other DMA
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channels have any work to do. If none of the channels
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have their DRQ lines asserted, the DMA controller has
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completed its work and will now tri-state the -MEMR,
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-MEMW, -IOR, -IOW and address signals.
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Finally, the DMA will de-assert the HRQ signal. The CPU
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sees this, and de-asserts the HOLDA signal. Now the CPU
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activates its -MEMR, -MEMW, -IOR, -IOW and address lines,
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and it resumes executing instructions and accessing main
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memory and the peripherals.
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For a typical floppy disk sector, the above process is
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repeated 512 times, once for each byte. Each time a byte
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is transferred, the address register in the DMA is
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incremented and the counter that shows how many bytes are
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to be transferred is decremented.
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When the counter reaches zero, the DMA asserts the EOP
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signal, which indicates that the counter has reached zero
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and no more data will be transferred until the DMA
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controller is reprogrammed by the CPU. This event is
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also called the Terminal Count (TC). There is only one
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EOP signal, because only one DMA channel can be active at
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any instant.
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If a peripheral wants to generate an interrupt when the
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transfer of a buffer is complete, it can test for its
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-DACK signal and the EOP signal both being asserted at
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the same time. When that happens, it means the DMA won't
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transfer any more information for that peripheral without
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intervention by the CPU. The peripheral can then assert
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one of the interrupt signals to get the processors'
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attention. The DMA chip itself is not capable of
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generating an interrupt. The peripheral and its
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associated hardware is responsible for generating any
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interrupt that occurs.
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It is important to understand that although the CPU
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always releases the bus to the DMA when the DMA makes the
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request, this action is invisible to both applications
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and the operating systems, except for slight changes in
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the amount of time the processor takes to execute
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instructions when the DMA is active. Subsequently, the
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processor must poll the peripheral, poll the registers in
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the DMA chip, or receive an interrupt from the peripheral
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to know for certain when a DMA transfer has completed.
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<sect1><heading>DMA Page Registers and 16Meg address space limitations</heading>
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<p>You may have noticed earlier that instead of the DMA
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setting the address lines to 0x00123456 as we said
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earlier, the DMA only set 0x3456. The reason for this
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takes a bit of explaining.
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When the original IBM PC was designed, IBM elected to use
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both DMA and interrupt controller chips that were
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designed for use with the 8085, an 8-bit processor with
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an address space of 16 bits (64K). Since the IBM PC
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supported more than 64K of memory, something had to be
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done to allow the DMA to read or write memory locations
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above the 64K mark. What IBM did to solve this problem
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was to add a latch for each DMA channel, that holds the
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upper bits of the address to be read to or written from.
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Whenever a DMA channel is active, the contents of that
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latch is written to the address bus and kept there until
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the DMA operation for the channel ends. These latches
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are called ``Page Registers''.
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So for our example above, the DMA would put the 0x3456
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part of the address on the bus, and the Page Register for
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DMA channel 2 would put 0x0012xxxx on the bus. Together,
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these two values form the complete address in memory that
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is to be accessed.
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Because the Page Register latch is independent of the DMA
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chip, the area of memory to be read or written must not
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span a 64K physical boundary. If the DMA accesses memory
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location 0xffff, the DMA will then increment the address
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register and it will access the next byte at 0x0000, not
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0x10000. The results of letting this happen are probably not intended.
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<quote><em>Note:</em> ``Physical'' 64K boundaries should
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not be confused with 8086-mode 64K ``Segments'', which
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are created by adding a segment register with an offset
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register. Page Registers have no address overlap.</quote>
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To further complicate matters, the external DMA address
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latches on the PC/AT hold only eight bits, so that gives
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us 8+16=24 bits, which means that the DMA can only point
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at memory locations between 0 and 16Meg. For newer
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computers that allow more than 16Meg of memory, the
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PC-compatible DMA cannot access locations above 16Meg.
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To get around this restriction, operating systems will
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reserve a buffer in an area below 16Meg that also doesn't
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span a physical 64K boundary. Then the DMA will be
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programmed to read data to that buffer. Once the DMA has
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moved the data into this buffer, the operating system
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will then copy the data from the buffer to the address
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where the data is really supposed to be stored.
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When writing data from an address above 16Meg to a
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DMA-based peripheral, the data must be first copied from
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where it resides into a buffer located below 16Meg, and
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then the DMA can copy the data from the buffer to the
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hardware. In FreeBSD, these reserved buffers are called
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``Bounce Buffers''. In the MS-DOS world, they are
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sometimes called ``Smart Buffers''.
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<sect1><heading>DMA Operational Modes and Settings</heading>
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<p>The 8237 DMA can be operated in several modes. The main
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ones are:
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<descrip>
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<tag/Single/ A single byte (or word) is transferred.
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The DMA must release and re-acquire the bus for each
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additional byte. This is commonly-used by devices
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that cannot transfer the entire block of data
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immediately. The peripheral will request the DMA
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each time it is ready for another transfer.
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The floppy disk controller only has a one-byte
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buffer, so it uses this mode.
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<tag>Block/Demand</tag> Once the DMA acquires the
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system bus, an entire block of data is transferred,
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up to a maximum of 64K. If the peripheral needs
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additional time, it can assert the READY signal.
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READY should not be used excessively, and for slow
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peripheral transfers, the Single Transfer Mode should
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be used instead.
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The difference between Block and Demand is the once a
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Block transfer is started, it runs until the transfer
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count reaches zero. DRQ only needs to be asserted
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until -DACK is asserted. Demand Mode will transfer
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one more bytes until DRQ is de-asserted, then when
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DRQ is asserted later, the transfer resumes where it
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was suspended.
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Older hard disk controllers used Demand Mode until
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CPU speeds increased to the point that it was more
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efficient to read the data using the CPU.
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<tag>Cascade</tag> This mechanism allows a DMA channel
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to request the bus, but then the attached peripheral
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device is responsible for placing addressing
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information on the bus. This is also known as ``Bus
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Mastering''.
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When a DMA channel in Cascade Mode receives control
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of the bus, the DMA does not place addresses and I/O
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control signals on the bus like it normally does.
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Instead, the DMA only asserts the -DACK signal for
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this channel.
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Now it is up to the device connected to that DMA
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channel to provide address and bus control signals.
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The peripheral has complete control over the system
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bus, and can do reads and/or writes to any address
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below 16Meg. When the peripheral is finished with
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bus, it de-asserts the DRQ line, and the DMA
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controller can return control to the CPU or to some
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other DMA channel.
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Cascade Mode can be used to chain multiple DMA
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controllers together, and this is exactly what DMA
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Channel 4 is used for in the PC. When a peripheral
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requests the bus on DMA channels 0, 1, 2 or 3, the
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slave DMA controller asserts HLDREQ, but this wire is
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actually connected to DRQ4 on the primary DMA
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controller. The primary DMA controller then requests
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the bus from the CPU using HLDREQ. Once the bus is
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granted, -DACK4 is asserted, and that wire is
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actually connected to the HLDA signal on the slave
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DMA controller. The slave DMA controller then
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transfers data for the DMA channel that requested it,
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or the slave DMA may grant the bus to a peripheral
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that wants to perform its own bus-mastering.
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Because of this wiring arrangement, only DMA channels
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0, 1, 2, 3, 5, 6 and 7 are usable on PC/AT systems.
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<quote><em>Note:</em> DMA channel 0 was reserved for
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refresh operations in early IBM PC computers, but
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is generally available for use by peripherals in
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modern systems.</quote>
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When a peripheral is performing Bus Mastering, it is
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important that the peripheral transmit data to or
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from memory constantly while it holds the system bus.
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If the peripheral cannot do this, it must release the
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bus frequently so that the system can perform refresh
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operations on memory.
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Since memory read and write cycles ``count'' as refresh
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cycles (a refresh cycle is actually an incomplete
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memory read cycle), as long as the peripheral
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controller continues reading or writing data to
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sequential memory locations, that action will refresh
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all of memory.
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Bus-mastering is found in some SCSI adapters and
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other high-performance peripheral cards.
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<tag>Autoinitialize</tag> This mode causes the DMA to
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perform Byte, Block or Demand transfers, but when the
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DMA transfer counter reaches zero, the counter and
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address is set back to where they were when the DMA
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channel was originally programmed. This means that
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as long as the device requests transfers, they will
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be granted. It is up to the CPU to move new data
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into the fixed buffer ahead of where the DMA is about
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to transfer it for output operations, and read new
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data out of the buffer behind where the DMA is
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writing on input operations. This technique is
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frequently used on audio devices that have small or
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no hardware ``sample'' buffers. There is additional
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CPU overhead to manage this ``circular'' buffer, but in
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some cases this may be the only way to eliminate the
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latency that occurs when the DMA counter reaches zero
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and the DMA stops until it is reprogrammed.
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</descrip>
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<sect1><heading>Programming the DMA</heading>
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<p>The DMA channel that is to be programmed should always
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be ``masked'' before loading any settings. This is because
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the hardware might assert DRQ, and the DMA might respond,
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even though not all of the parameters have been loaded or
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updated.
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Once masked, the host must specify the direction of the
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transfer (memory-to-I/O or I/O-to-memory), what mode of
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DMA operation is to be used for the transfer (Single,
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Block, Demand, Cascade, etc), and finally the address and
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length of the transfer are loaded. The length that is
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loaded is one less than the amount you expect the DMA to
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transfer. The LSB and MSB of the address and length are
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written to the same 8-bit I/O port, so another port must
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be written to first to guarantee that the DMA accepts the
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first byte as the LSB and the second byte as the MSB.
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Then, be sure to update the Page Register, which is
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external to the DMA and is accessed through a different
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set of I/O ports.
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Once all the settings are ready, the DMA channel can be
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un-masked. That DMA channel is now considered to be
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``armed'', and will respond when DRQ is asserted.
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Refer to a hardware data book for precise programming
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details for the 8237. You will also need to refer to the
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I/O port map for the PC system. This map describes where
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the DMA and Page Register ports are located. A complete
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table is located below.
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<sect1><heading>DMA Port Map</heading>
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<p>All systems based on the IBM-PC and PC/AT have the DMA
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hardware located at the same I/O ports. The complete
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list is provided below. Ports assigned to DMA Controller
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#2 are undefined on non-AT designs.
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<sect2><heading>0x00 - 0x1f DMA Controller #1 (Channels 0, 1, 2 and 3)</heading>
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<p>DMA Address and Count Registers
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<verb>
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0x00 write Channel 0 starting address
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0x00 read Channel 0 current address
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0x02 write Channel 0 starting word count
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0x02 read Channel 0 remaining word count
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0x04 write Channel 1 starting address
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0x04 read Channel 1 current address
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0x06 write Channel 1 starting word count
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0x06 read Channel 1 remaining word count
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0x08 write Channel 2 starting address
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0x08 read Channel 2 current address
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0x0a write Channel 2 starting word count
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0x0a read Channel 2 remaining word count
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0x0c write Channel 3 starting address
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0x0c read Channel 3 current address
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0x0e write Channel 3 starting word count
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0x0e read Channel 3 remaining word count
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</verb>
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DMA Command Registers
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<verb>
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0x10 write Command Register
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0x10 read Status Register
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0x12 write Request Register
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0x12 read -
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0x14 write Single Mask Register Bit
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0x14 read -
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0x16 write Mode Register
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0x16 read -
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0x18 write Clear LSB/MSB Flip-Flop
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0x18 read -
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0x1a write Master Clear/Reset
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0x1a read Temporary Register
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0x1c write Clear Mask Register
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0x1c read -
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0x1e write Write All Mask Register Bits
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0x1e read -
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</verb>
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<sect2><heading>0xc0 - 0xdf DMA Controller #2 (Channels 4, 5, 6 and 7)</heading>
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<p>DMA Address and Count Registers
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<verb>
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0xc0 write Channel 4 starting address
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0xc0 read Channel 4 current address
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0xc2 write Channel 4 starting word count
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0xc2 read Channel 4 remaining word count
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0xc4 write Channel 5 starting address
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0xc4 read Channel 5 current address
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0xc6 write Channel 5 starting word count
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0xc6 read Channel 5 remaining word count
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0xc8 write Channel 6 starting address
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0xc8 read Channel 6 current address
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0xca write Channel 6 starting word count
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0xca read Channel 6 remaining word count
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0xcc write Channel 7 starting address
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0xcc read Channel 7 current address
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0xce write Channel 7 starting word count
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0xce read Channel 7 remaining word count
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</verb>
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DMA Command Registers
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<verb>
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0xd0 write Command Register
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0xd0 read Status Register
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0xd2 write Request Register
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0xd2 read -
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0xd4 write Single Mask Register Bit
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0xd4 read -
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0xd6 write Mode Register
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0xd6 read -
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0xd8 write Clear LSB/MSB Flip-Flop
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0xd8 read -
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0xda write Master Clear/Reset
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0xda read Temporary Register
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0xdc write Clear Mask Register
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0xdc read -
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0xde write Write All Mask Register Bits
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0xde read -
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</verb>
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<sect2><heading>0x80 - 0x9f DMA Page Registers</heading>
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<p><verb>
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0x87 r/w DMA Channel 0
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0x83 r/w DMA Channel 1
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0x81 r/w DMA Channel 2
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0x82 r/w DMA Channel 3
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0x8b r/w DMA Channel 5
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0x89 r/w DMA Channel 6
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0x8a r/w DMA Channel 7
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0x8f Refresh
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</verb>
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