eb69ed7f87
Intel® Arria® 10 SoC. Cadence Quad SPI Flash is not generic SPI controller, but SPI flash controller, so don't use spibus here, instead provide quad spi flash interface. Since it is not on spibus, then mx25l flash device driver is not usable here, so provide new n25q flash device driver with quad spi flash interface. Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D10245
135 lines
6.4 KiB
C
135 lines
6.4 KiB
C
/*-
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* Copyright (c) 2017-2018 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _CQSPI_H_
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#define _CQSPI_H_
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#define CQSPI_CFG 0x00 /* QSPI Configuration */
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#define CFG_IDLE (1 << 31)
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#define CFG_ENDMA (1 << 15)
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#define CFG_IDLE (1 << 31)
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#define CFG_BAUD_S 19
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#define CFG_BAUD_M (0xf << CFG_BAUD_S)
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#define CFG_BAUD2 (0 << CFG_BAUD_S)
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#define CFG_BAUD4 (1 << CFG_BAUD_S)
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#define CFG_BAUD6 (2 << CFG_BAUD_S)
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#define CFG_BAUD8 (3 << CFG_BAUD_S)
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#define CFG_BAUD10 (4 << CFG_BAUD_S)
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#define CFG_BAUD12 (5 << CFG_BAUD_S)
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#define CFG_BAUD14 (6 << CFG_BAUD_S)
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#define CFG_BAUD16 (7 << CFG_BAUD_S)
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#define CFG_BAUD18 (8 << CFG_BAUD_S)
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#define CFG_BAUD20 (9 << CFG_BAUD_S)
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#define CFG_BAUD22 (10 << CFG_BAUD_S)
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#define CFG_BAUD24 (11 << CFG_BAUD_S)
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#define CFG_BAUD26 (12 << CFG_BAUD_S)
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#define CFG_BAUD28 (13 << CFG_BAUD_S)
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#define CFG_BAUD30 (14 << CFG_BAUD_S)
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#define CFG_BAUD32 (0xf << CFG_BAUD_S)
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#define CFG_EN (1 << 0)
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#define CQSPI_DEVRD 0x04 /* Device Read Instruction Configuration */
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#define DEVRD_DUMMYRDCLKS_S 24
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#define DEVRD_ENMODEBITS (1 << 20)
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#define DEVRD_DATA_WIDTH_S 16
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#define DEVRD_DATA_WIDTH_QUAD (2 << DEVRD_DATA_WIDTH_S)
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#define DEVRD_ADDR_WIDTH_S 12
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#define DEVRD_ADDR_WIDTH_SINGLE (0 << DEVRD_ADDR_WIDTH_S)
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#define DEVRD_INST_WIDTH_S 8
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#define DEVRD_INST_WIDTH_SINGLE (0 << DEVRD_INST_WIDTH_S)
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#define DEVRD_RDOPCODE_S 0
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#define CQSPI_DEVWR 0x08 /* Device Write Instruction Configuration */
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#define DEVWR_DUMMYWRCLKS_S 24
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#define DEVWR_WROPCODE_S 0
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#define DEVWR_DATA_WIDTH_S 16
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#define DEVWR_DATA_WIDTH_QUAD (2 << DEVWR_DATA_WIDTH_S)
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#define DEVWR_ADDR_WIDTH_S 12
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#define DEVWR_ADDR_WIDTH_SINGLE (0 << DEVWR_ADDR_WIDTH_S)
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#define CQSPI_DELAY 0x0C /* QSPI Device Delay Register */
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#define DELAY_NSS_S 24
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#define DELAY_BTWN_S 16
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#define DELAY_AFTER_S 8
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#define DELAY_INIT_S 0
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#define CQSPI_RDDATACAP 0x10 /* Read Data Capture Register */
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#define RDDATACAP_DELAY_S 1
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#define RDDATACAP_DELAY_M (0xf << RDDATACAP_DELAY_S)
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#define CQSPI_DEVSZ 0x14 /* Device Size Configuration Register */
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#define DEVSZ_NUMADDRBYTES_S 0
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#define DEVSZ_NUMADDRBYTES_M (0xf << DEVSZ_NUMADDRBYTES_S)
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#define CQSPI_SRAMPART 0x18 /* SRAM Partition Configuration Register */
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#define CQSPI_INDADDRTRIG 0x1C /* Indirect AHB Address Trigger Register */
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#define CQSPI_DMAPER 0x20 /* DMA Peripheral Configuration Register */
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#define DMAPER_NUMSGLREQBYTES_S 0
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#define DMAPER_NUMBURSTREQBYTES_S 8
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#define DMAPER_NUMSGLREQBYTES_4 (2 << DMAPER_NUMSGLREQBYTES_S);
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#define DMAPER_NUMBURSTREQBYTES_4 (2 << DMAPER_NUMBURSTREQBYTES_S);
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#define CQSPI_REMAPADDR 0x24 /* Remap Address Register */
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#define CQSPI_MODEBIT 0x28 /* Mode Bit Configuration */
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#define CQSPI_SRAMFILL 0x2C /* SRAM Fill Register */
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#define CQSPI_TXTHRESH 0x30 /* TX Threshold Register */
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#define CQSPI_RXTHRESH 0x34 /* RX Threshold Register */
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#define CQSPI_IRQSTAT 0x40 /* Interrupt Status Register */
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#define CQSPI_IRQMASK 0x44 /* Interrupt Mask */
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#define IRQMASK_INDSRAMFULL (1 << 12)
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#define IRQMASK_INDXFRLVL (1 << 6)
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#define IRQMASK_INDOPDONE (1 << 2)
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#define CQSPI_LOWWRPROT 0x50 /* Lower Write Protection */
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#define CQSPI_UPPWRPROT 0x54 /* Upper Write Protection */
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#define CQSPI_WRPROT 0x58 /* Write Protection Control Register */
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#define CQSPI_INDRD 0x60 /* Indirect Read Transfer Control Register */
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#define INDRD_IND_OPS_DONE_STATUS (1 << 5)
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#define INDRD_START (1 << 0)
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#define CQSPI_INDRDWATER 0x64 /* Indirect Read Transfer Watermark Register */
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#define CQSPI_INDRDSTADDR 0x68 /* Indirect Read Transfer Start Address Register */
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#define CQSPI_INDRDCNT 0x6C /* Indirect Read Transfer Number Bytes Register */
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#define CQSPI_INDWR 0x70 /* Indirect Write Transfer Control Register */
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#define CQSPI_INDWRWATER 0x74 /* Indirect Write Transfer Watermark Register */
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#define CQSPI_INDWRSTADDR 0x78 /* Indirect Write Transfer Start Address Register */
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#define CQSPI_INDWRCNT 0x7C /* Indirect Write Transfer Number Bytes Register */
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#define CQSPI_FLASHCMD 0x90 /* Flash Command Control Register */
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#define FLASHCMD_NUMADDRBYTES_S 16
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#define FLASHCMD_NUMRDDATABYTES_S 20
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#define FLASHCMD_NUMRDDATABYTES_M (0x7 << FLASHCMD_NUMRDDATABYTES_S)
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#define FLASHCMD_ENCMDADDR (1 << 19)
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#define FLASHCMD_ENRDDATA (1 << 23)
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#define FLASHCMD_CMDOPCODE_S 24
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#define FLASHCMD_CMDOPCODE_M (0xff << FLASHCMD_CMDOPCODE_S)
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#define FLASHCMD_CMDEXECSTAT (1 << 1) /* Command execution in progress. */
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#define FLASHCMD_EXECCMD (1 << 0) /* Execute the command. */
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#define CQSPI_FLASHCMDADDR 0x94 /* Flash Command Address Registers */
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#define CQSPI_FLASHCMDRDDATALO 0xA0 /* Flash Command Read Data Register (Lower) */
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#define CQSPI_FLASHCMDRDDATAUP 0xA4 /* Flash Command Read Data Register (Upper) */
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#define CQSPI_FLASHCMDWRDATALO 0xA8 /* Flash Command Write Data Register (Lower) */
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#define CQSPI_FLASHCMDWRDATAUP 0xAC /* Flash Command Write Data Register (Upper) */
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#define CQSPI_MODULEID 0xFC /* Module ID Register */
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#endif /* !_CQSPI_H_ */
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