671 lines
17 KiB
C
671 lines
17 KiB
C
/*
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* Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2004 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ah_desc.h"
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#include "ar5210/ar5210.h"
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#include "ar5210/ar5210reg.h"
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#include "ar5210/ar5210phy.h"
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#include "ar5210/ar5210desc.h"
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/*
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* Set the properties of the tx queue with the parameters
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* from qInfo. The queue must previously have been setup
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* with a call to ar5210SetupTxQueue.
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*/
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HAL_BOOL
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ar5210SetTxQueueProps(struct ath_hal *ah, int q, const HAL_TXQ_INFO *qInfo)
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{
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struct ath_hal_5210 *ahp = AH5210(ah);
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if (q >= HAL_NUM_TX_QUEUES) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
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__func__, q);
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return AH_FALSE;
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}
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return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], qInfo);
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}
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/*
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* Return the properties for the specified tx queue.
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*/
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HAL_BOOL
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ar5210GetTxQueueProps(struct ath_hal *ah, int q, HAL_TXQ_INFO *qInfo)
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{
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struct ath_hal_5210 *ahp = AH5210(ah);
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if (q >= HAL_NUM_TX_QUEUES) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
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__func__, q);
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return AH_FALSE;
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}
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return ath_hal_getTxQProps(ah, qInfo, &ahp->ah_txq[q]);
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}
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/*
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* Allocate and initialize a tx DCU/QCU combination.
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*/
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int
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ar5210SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
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const HAL_TXQ_INFO *qInfo)
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{
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struct ath_hal_5210 *ahp = AH5210(ah);
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HAL_TX_QUEUE_INFO *qi;
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int q;
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switch (type) {
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case HAL_TX_QUEUE_BEACON:
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q = 2;
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break;
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case HAL_TX_QUEUE_CAB:
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q = 1;
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break;
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case HAL_TX_QUEUE_DATA:
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q = 0;
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break;
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default:
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad tx queue type %u\n",
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__func__, type);
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return -1;
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}
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HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
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qi = &ahp->ah_txq[q];
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if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: tx queue %u already active\n",
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__func__, q);
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return -1;
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}
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OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO));
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qi->tqi_type = type;
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if (qInfo == AH_NULL) {
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/* by default enable OK+ERR+DESC+URN interrupts */
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qi->tqi_qflags =
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HAL_TXQ_TXOKINT_ENABLE
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| HAL_TXQ_TXERRINT_ENABLE
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| HAL_TXQ_TXDESCINT_ENABLE
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| HAL_TXQ_TXURNINT_ENABLE
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;
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qi->tqi_aifs = INIT_AIFS;
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qi->tqi_cwmin = HAL_TXQ_USEDEFAULT; /* NB: do at reset */
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qi->tqi_shretry = INIT_SH_RETRY;
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qi->tqi_lgretry = INIT_LG_RETRY;
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} else
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(void) ar5210SetTxQueueProps(ah, q, qInfo);
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/* NB: must be followed by ar5210ResetTxQueue */
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return q;
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}
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/*
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* Free a tx DCU/QCU combination.
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*/
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HAL_BOOL
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ar5210ReleaseTxQueue(struct ath_hal *ah, u_int q)
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{
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struct ath_hal_5210 *ahp = AH5210(ah);
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HAL_TX_QUEUE_INFO *qi;
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if (q >= HAL_NUM_TX_QUEUES) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
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__func__, q);
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return AH_FALSE;
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}
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qi = &ahp->ah_txq[q];
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if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
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HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
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__func__, q);
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return AH_FALSE;
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}
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HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: release queue %u\n", __func__, q);
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qi->tqi_type = HAL_TX_QUEUE_INACTIVE;
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ahp->ah_txOkInterruptMask &= ~(1 << q);
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ahp->ah_txErrInterruptMask &= ~(1 << q);
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ahp->ah_txDescInterruptMask &= ~(1 << q);
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ahp->ah_txEolInterruptMask &= ~(1 << q);
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ahp->ah_txUrnInterruptMask &= ~(1 << q);
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return AH_TRUE;
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#undef N
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}
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HAL_BOOL
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ar5210ResetTxQueue(struct ath_hal *ah, u_int q)
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{
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struct ath_hal_5210 *ahp = AH5210(ah);
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const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
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HAL_TX_QUEUE_INFO *qi;
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uint32_t cwMin;
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if (q >= HAL_NUM_TX_QUEUES) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
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__func__, q);
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return AH_FALSE;
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}
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qi = &ahp->ah_txq[q];
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if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
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HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
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__func__, q);
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return AH_FALSE;
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}
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/*
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* Ignore any non-data queue(s).
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*/
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if (qi->tqi_type != HAL_TX_QUEUE_DATA)
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return AH_TRUE;
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/* Set turbo mode / base mode parameters on or off */
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if (IEEE80211_IS_CHAN_TURBO(chan)) {
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OS_REG_WRITE(ah, AR_SLOT_TIME, INIT_SLOT_TIME_TURBO);
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OS_REG_WRITE(ah, AR_TIME_OUT, INIT_ACK_CTS_TIMEOUT_TURBO);
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OS_REG_WRITE(ah, AR_USEC, INIT_TRANSMIT_LATENCY_TURBO);
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OS_REG_WRITE(ah, AR_IFS0,
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((INIT_SIFS_TURBO + qi->tqi_aifs * INIT_SLOT_TIME_TURBO)
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<< AR_IFS0_DIFS_S)
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| INIT_SIFS_TURBO);
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OS_REG_WRITE(ah, AR_IFS1, INIT_PROTO_TIME_CNTRL_TURBO);
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OS_REG_WRITE(ah, AR_PHY(17),
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(OS_REG_READ(ah, AR_PHY(17)) & ~0x7F) | 0x38);
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OS_REG_WRITE(ah, AR_PHY_FRCTL,
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AR_PHY_SERVICE_ERR | AR_PHY_TXURN_ERR |
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AR_PHY_ILLLEN_ERR | AR_PHY_ILLRATE_ERR |
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AR_PHY_PARITY_ERR | AR_PHY_TIMING_ERR |
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0x2020 |
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AR_PHY_TURBO_MODE | AR_PHY_TURBO_SHORT);
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} else {
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OS_REG_WRITE(ah, AR_SLOT_TIME, INIT_SLOT_TIME);
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OS_REG_WRITE(ah, AR_TIME_OUT, INIT_ACK_CTS_TIMEOUT);
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OS_REG_WRITE(ah, AR_USEC, INIT_TRANSMIT_LATENCY);
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OS_REG_WRITE(ah, AR_IFS0,
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((INIT_SIFS + qi->tqi_aifs * INIT_SLOT_TIME)
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<< AR_IFS0_DIFS_S)
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| INIT_SIFS);
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OS_REG_WRITE(ah, AR_IFS1, INIT_PROTO_TIME_CNTRL);
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OS_REG_WRITE(ah, AR_PHY(17),
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(OS_REG_READ(ah, AR_PHY(17)) & ~0x7F) | 0x1C);
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OS_REG_WRITE(ah, AR_PHY_FRCTL,
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AR_PHY_SERVICE_ERR | AR_PHY_TXURN_ERR |
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AR_PHY_ILLLEN_ERR | AR_PHY_ILLRATE_ERR |
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AR_PHY_PARITY_ERR | AR_PHY_TIMING_ERR | 0x1020);
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}
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if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT)
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cwMin = INIT_CWMIN;
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else
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cwMin = qi->tqi_cwmin;
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/* Set cwmin and retry limit values */
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OS_REG_WRITE(ah, AR_RETRY_LMT,
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(cwMin << AR_RETRY_LMT_CW_MIN_S)
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| SM(INIT_SLG_RETRY, AR_RETRY_LMT_SLG_RETRY)
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| SM(INIT_SSH_RETRY, AR_RETRY_LMT_SSH_RETRY)
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| SM(qi->tqi_lgretry, AR_RETRY_LMT_LG_RETRY)
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| SM(qi->tqi_shretry, AR_RETRY_LMT_SH_RETRY)
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);
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if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE)
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ahp->ah_txOkInterruptMask |= 1 << q;
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else
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ahp->ah_txOkInterruptMask &= ~(1 << q);
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if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE)
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ahp->ah_txErrInterruptMask |= 1 << q;
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else
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ahp->ah_txErrInterruptMask &= ~(1 << q);
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if (qi->tqi_qflags & HAL_TXQ_TXDESCINT_ENABLE)
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ahp->ah_txDescInterruptMask |= 1 << q;
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else
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ahp->ah_txDescInterruptMask &= ~(1 << q);
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if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE)
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ahp->ah_txEolInterruptMask |= 1 << q;
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else
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ahp->ah_txEolInterruptMask &= ~(1 << q);
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if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE)
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ahp->ah_txUrnInterruptMask |= 1 << q;
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else
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ahp->ah_txUrnInterruptMask &= ~(1 << q);
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return AH_TRUE;
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}
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/*
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* Get the TXDP for the "main" data queue. Needs to be extended
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* for multiple Q functionality
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*/
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uint32_t
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ar5210GetTxDP(struct ath_hal *ah, u_int q)
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{
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struct ath_hal_5210 *ahp = AH5210(ah);
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HAL_TX_QUEUE_INFO *qi;
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HALASSERT(q < HAL_NUM_TX_QUEUES);
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qi = &ahp->ah_txq[q];
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switch (qi->tqi_type) {
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case HAL_TX_QUEUE_DATA:
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return OS_REG_READ(ah, AR_TXDP0);
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case HAL_TX_QUEUE_INACTIVE:
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: inactive queue %u\n",
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__func__, q);
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/* fall thru... */
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default:
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break;
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}
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return 0xffffffff;
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}
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/*
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* Set the TxDP for the "main" data queue.
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*/
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HAL_BOOL
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ar5210SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp)
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{
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struct ath_hal_5210 *ahp = AH5210(ah);
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HAL_TX_QUEUE_INFO *qi;
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HALASSERT(q < HAL_NUM_TX_QUEUES);
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HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u 0x%x\n",
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__func__, q, txdp);
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qi = &ahp->ah_txq[q];
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switch (qi->tqi_type) {
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case HAL_TX_QUEUE_DATA:
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#ifdef AH_DEBUG
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/*
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* Make sure that TXE is deasserted before setting the
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* TXDP. If TXE is still asserted, setting TXDP will
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* have no effect.
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*/
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if (OS_REG_READ(ah, AR_CR) & AR_CR_TXE0)
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ath_hal_printf(ah, "%s: TXE asserted; AR_CR=0x%x\n",
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__func__, OS_REG_READ(ah, AR_CR));
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#endif
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OS_REG_WRITE(ah, AR_TXDP0, txdp);
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break;
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case HAL_TX_QUEUE_BEACON:
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case HAL_TX_QUEUE_CAB:
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OS_REG_WRITE(ah, AR_TXDP1, txdp);
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break;
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case HAL_TX_QUEUE_INACTIVE:
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HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
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__func__, q);
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/* fall thru... */
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default:
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return AH_FALSE;
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}
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return AH_TRUE;
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}
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/*
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* Update Tx FIFO trigger level.
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*
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* Set bIncTrigLevel to TRUE to increase the trigger level.
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* Set bIncTrigLevel to FALSE to decrease the trigger level.
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*
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* Returns TRUE if the trigger level was updated
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*/
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HAL_BOOL
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ar5210UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
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{
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uint32_t curTrigLevel;
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HAL_INT ints = ar5210GetInterrupts(ah);
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/*
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* Disable chip interrupts. This is because halUpdateTxTrigLevel
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* is called from both ISR and non-ISR contexts.
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*/
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(void) ar5210SetInterrupts(ah, ints &~ HAL_INT_GLOBAL);
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curTrigLevel = OS_REG_READ(ah, AR_TRIG_LEV);
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if (bIncTrigLevel){
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/* increase the trigger level */
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curTrigLevel = curTrigLevel +
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((MAX_TX_FIFO_THRESHOLD - curTrigLevel) / 2);
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} else {
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/* decrease the trigger level if not already at the minimum */
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if (curTrigLevel > MIN_TX_FIFO_THRESHOLD) {
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/* decrease the trigger level */
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curTrigLevel--;
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} else {
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/* no update to the trigger level */
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/* re-enable chip interrupts */
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ar5210SetInterrupts(ah, ints);
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return AH_FALSE;
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}
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}
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/* Update the trigger level */
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OS_REG_WRITE(ah, AR_TRIG_LEV, curTrigLevel);
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/* re-enable chip interrupts */
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ar5210SetInterrupts(ah, ints);
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return AH_TRUE;
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}
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/*
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* Set Transmit Enable bits for the specified queues.
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*/
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HAL_BOOL
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ar5210StartTxDma(struct ath_hal *ah, u_int q)
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{
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struct ath_hal_5210 *ahp = AH5210(ah);
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HAL_TX_QUEUE_INFO *qi;
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HALASSERT(q < HAL_NUM_TX_QUEUES);
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HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
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qi = &ahp->ah_txq[q];
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switch (qi->tqi_type) {
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case HAL_TX_QUEUE_DATA:
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OS_REG_WRITE(ah, AR_CR, AR_CR_TXE0);
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break;
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case HAL_TX_QUEUE_CAB:
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OS_REG_WRITE(ah, AR_CR, AR_CR_TXE1); /* enable altq xmit */
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OS_REG_WRITE(ah, AR_BCR,
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AR_BCR_TQ1V | AR_BCR_BDMAE | AR_BCR_TQ1FV);
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break;
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case HAL_TX_QUEUE_BEACON:
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/* XXX add CR_BCR_BCMD if IBSS mode */
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OS_REG_WRITE(ah, AR_BCR, AR_BCR_TQ1V | AR_BCR_BDMAE);
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break;
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case HAL_TX_QUEUE_INACTIVE:
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: inactive queue %u\n",
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__func__, q);
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/* fal thru... */
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default:
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return AH_FALSE;
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}
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return AH_TRUE;
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}
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uint32_t
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ar5210NumTxPending(struct ath_hal *ah, u_int q)
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{
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struct ath_hal_5210 *ahp = AH5210(ah);
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HAL_TX_QUEUE_INFO *qi;
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uint32_t v;
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HALASSERT(q < HAL_NUM_TX_QUEUES);
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HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
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qi = &ahp->ah_txq[q];
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switch (qi->tqi_type) {
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case HAL_TX_QUEUE_DATA:
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v = OS_REG_READ(ah, AR_CFG);
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return MS(v, AR_CFG_TXCNT);
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case HAL_TX_QUEUE_INACTIVE:
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: inactive queue %u\n",
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__func__, q);
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/* fall thru... */
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default:
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break;
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}
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return 0;
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}
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/*
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* Stop transmit on the specified queue
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*/
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HAL_BOOL
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ar5210StopTxDma(struct ath_hal *ah, u_int q)
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{
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struct ath_hal_5210 *ahp = AH5210(ah);
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HAL_TX_QUEUE_INFO *qi;
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HALASSERT(q < HAL_NUM_TX_QUEUES);
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HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
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qi = &ahp->ah_txq[q];
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switch (qi->tqi_type) {
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case HAL_TX_QUEUE_DATA: {
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int i;
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OS_REG_WRITE(ah, AR_CR, AR_CR_TXD0);
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for (i = 0; i < 1000; i++) {
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if ((OS_REG_READ(ah, AR_CFG) & AR_CFG_TXCNT) == 0)
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break;
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OS_DELAY(10);
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}
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OS_REG_WRITE(ah, AR_CR, 0);
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return (i < 1000);
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}
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case HAL_TX_QUEUE_BEACON:
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return ath_hal_wait(ah, AR_BSR, AR_BSR_TXQ1F, 0);
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case HAL_TX_QUEUE_INACTIVE:
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: inactive queue %u\n",
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__func__, q);
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/* fall thru... */
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default:
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break;
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}
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return AH_FALSE;
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}
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/*
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* Descriptor Access Functions
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*/
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|
|
|
#define VALID_PKT_TYPES \
|
|
((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\
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|
(1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\
|
|
(1<<HAL_PKT_TYPE_BEACON))
|
|
#define isValidPktType(_t) ((1<<(_t)) & VALID_PKT_TYPES)
|
|
#define VALID_TX_RATES \
|
|
((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\
|
|
(1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\
|
|
(1<<0x1d)|(1<<0x18)|(1<<0x1c))
|
|
#define isValidTxRate(_r) ((1<<(_r)) & VALID_TX_RATES)
|
|
|
|
HAL_BOOL
|
|
ar5210SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
|
|
u_int pktLen,
|
|
u_int hdrLen,
|
|
HAL_PKT_TYPE type,
|
|
u_int txPower,
|
|
u_int txRate0, u_int txTries0,
|
|
u_int keyIx,
|
|
u_int antMode,
|
|
u_int flags,
|
|
u_int rtsctsRate,
|
|
u_int rtsctsDuration,
|
|
u_int compicvLen,
|
|
u_int compivLen,
|
|
u_int comp)
|
|
{
|
|
struct ar5210_desc *ads = AR5210DESC(ds);
|
|
uint32_t frtype;
|
|
|
|
(void) txPower;
|
|
(void) rtsctsDuration;
|
|
|
|
HALASSERT(txTries0 != 0);
|
|
HALASSERT(isValidPktType(type));
|
|
HALASSERT(isValidTxRate(txRate0));
|
|
|
|
if (type == HAL_PKT_TYPE_BEACON || type == HAL_PKT_TYPE_PROBE_RESP)
|
|
frtype = AR_Frm_NoDelay;
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|
else
|
|
frtype = type << 26;
|
|
ads->ds_ctl0 = (pktLen & AR_FrameLen)
|
|
| (txRate0 << AR_XmitRate_S)
|
|
| ((hdrLen << AR_HdrLen_S) & AR_HdrLen)
|
|
| frtype
|
|
| (flags & HAL_TXDESC_CLRDMASK ? AR_ClearDestMask : 0)
|
|
| (flags & HAL_TXDESC_INTREQ ? AR_TxInterReq : 0)
|
|
| (antMode ? AR_AntModeXmit : 0)
|
|
;
|
|
if (keyIx != HAL_TXKEYIX_INVALID) {
|
|
ads->ds_ctl1 = (keyIx << AR_EncryptKeyIdx_S) & AR_EncryptKeyIdx;
|
|
ads->ds_ctl0 |= AR_EncryptKeyValid;
|
|
} else
|
|
ads->ds_ctl1 = 0;
|
|
if (flags & HAL_TXDESC_RTSENA) {
|
|
ads->ds_ctl0 |= AR_RTSCTSEnable;
|
|
ads->ds_ctl1 |= (rtsctsDuration << AR_RTSDuration_S)
|
|
& AR_RTSDuration;
|
|
}
|
|
return AH_TRUE;
|
|
}
|
|
|
|
HAL_BOOL
|
|
ar5210SetupXTxDesc(struct ath_hal *ah, struct ath_desc *ds,
|
|
u_int txRate1, u_int txTries1,
|
|
u_int txRate2, u_int txTries2,
|
|
u_int txRate3, u_int txTries3)
|
|
{
|
|
(void) ah; (void) ds;
|
|
(void) txRate1; (void) txTries1;
|
|
(void) txRate2; (void) txTries2;
|
|
(void) txRate3; (void) txTries3;
|
|
return AH_FALSE;
|
|
}
|
|
|
|
void
|
|
ar5210IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *ds)
|
|
{
|
|
struct ar5210_desc *ads = AR5210DESC(ds);
|
|
|
|
ads->ds_ctl0 |= AR_TxInterReq;
|
|
}
|
|
|
|
HAL_BOOL
|
|
ar5210FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
|
|
HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, u_int descId,
|
|
u_int qcuId, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
|
|
const struct ath_desc *ds0)
|
|
{
|
|
struct ar5210_desc *ads = AR5210DESC(ds);
|
|
uint32_t segLen = segLenList[0];
|
|
|
|
HALASSERT((segLen &~ AR_BufLen) == 0);
|
|
|
|
ds->ds_data = bufAddrList[0];
|
|
|
|
if (firstSeg) {
|
|
/*
|
|
* First descriptor, don't clobber xmit control data
|
|
* setup by ar5210SetupTxDesc.
|
|
*/
|
|
ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_More);
|
|
} else if (lastSeg) { /* !firstSeg && lastSeg */
|
|
/*
|
|
* Last descriptor in a multi-descriptor frame,
|
|
* copy the transmit parameters from the first
|
|
* frame for processing on completion.
|
|
*/
|
|
ads->ds_ctl0 = AR5210DESC_CONST(ds0)->ds_ctl0;
|
|
ads->ds_ctl1 = segLen;
|
|
} else { /* !firstSeg && !lastSeg */
|
|
/*
|
|
* Intermediate descriptor in a multi-descriptor frame.
|
|
*/
|
|
ads->ds_ctl0 = 0;
|
|
ads->ds_ctl1 = segLen | AR_More;
|
|
}
|
|
ads->ds_status0 = ads->ds_status1 = 0;
|
|
return AH_TRUE;
|
|
}
|
|
|
|
/*
|
|
* Processing of HW TX descriptor.
|
|
*/
|
|
HAL_STATUS
|
|
ar5210ProcTxDesc(struct ath_hal *ah,
|
|
struct ath_desc *ds, struct ath_tx_status *ts)
|
|
{
|
|
struct ar5210_desc *ads = AR5210DESC(ds);
|
|
|
|
if ((ads->ds_status1 & AR_Done) == 0)
|
|
return HAL_EINPROGRESS;
|
|
|
|
/* Update software copies of the HW status */
|
|
ts->ts_seqnum = ads->ds_status1 & AR_SeqNum;
|
|
ts->ts_tstamp = MS(ads->ds_status0, AR_SendTimestamp);
|
|
ts->ts_status = 0;
|
|
if ((ads->ds_status0 & AR_FrmXmitOK) == 0) {
|
|
if (ads->ds_status0 & AR_ExcessiveRetries)
|
|
ts->ts_status |= HAL_TXERR_XRETRY;
|
|
if (ads->ds_status0 & AR_Filtered)
|
|
ts->ts_status |= HAL_TXERR_FILT;
|
|
if (ads->ds_status0 & AR_FIFOUnderrun)
|
|
ts->ts_status |= HAL_TXERR_FIFO;
|
|
}
|
|
ts->ts_rate = MS(ads->ds_ctl0, AR_XmitRate);
|
|
ts->ts_rssi = MS(ads->ds_status1, AR_AckSigStrength);
|
|
ts->ts_shortretry = MS(ads->ds_status0, AR_ShortRetryCnt);
|
|
ts->ts_longretry = MS(ads->ds_status0, AR_LongRetryCnt);
|
|
ts->ts_antenna = 0; /* NB: don't know */
|
|
ts->ts_finaltsi = 0;
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/*
|
|
* Determine which tx queues need interrupt servicing.
|
|
* STUB.
|
|
*/
|
|
void
|
|
ar5210GetTxIntrQueue(struct ath_hal *ah, uint32_t *txqs)
|
|
{
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Retrieve the rate table from the given TX completion descriptor
|
|
*/
|
|
HAL_BOOL
|
|
ar5210GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int *rates, int *tries)
|
|
{
|
|
return AH_FALSE;
|
|
}
|
|
|
|
/*
|
|
* Set the TX descriptor link pointer
|
|
*/
|
|
void
|
|
ar5210SetTxDescLink(struct ath_hal *ah, void *ds, uint32_t link)
|
|
{
|
|
struct ar5210_desc *ads = AR5210DESC(ds);
|
|
|
|
ads->ds_link = link;
|
|
}
|
|
|
|
/*
|
|
* Get the TX descriptor link pointer
|
|
*/
|
|
void
|
|
ar5210GetTxDescLink(struct ath_hal *ah, void *ds, uint32_t *link)
|
|
{
|
|
struct ar5210_desc *ads = AR5210DESC(ds);
|
|
|
|
*link = ads->ds_link;
|
|
}
|
|
|
|
/*
|
|
* Get a pointer to the TX descriptor link pointer
|
|
*/
|
|
void
|
|
ar5210GetTxDescLinkPtr(struct ath_hal *ah, void *ds, uint32_t **linkptr)
|
|
{
|
|
struct ar5210_desc *ads = AR5210DESC(ds);
|
|
|
|
*linkptr = &ads->ds_link;
|
|
}
|