4160ed6f8b
r354266 changed the type of bp_kernload to vm_paddr_t in platform_mpc85xx.c, but not the variable itself in locore.S. This caused the AP to not come up, due to overwriting the following variable (bp_virtaddr). Also, properly load bp_kernload into MAS3 and MAS7. Prior to r354266, we required loading into the low 4GB, but now we can load from anywhere in memory that ubldr can access.
970 lines
21 KiB
ArmAsm
970 lines
21 KiB
ArmAsm
/*-
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* Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
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* Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include "assym.inc"
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#include "opt_hwpmc_hooks.h"
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#include <machine/asm.h>
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#include <machine/hid.h>
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#include <machine/param.h>
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#include <machine/spr.h>
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#include <machine/pte.h>
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#include <machine/trap.h>
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#include <machine/vmparam.h>
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#include <machine/tlb.h>
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#ifdef _CALL_ELF
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.abiversion _CALL_ELF
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#endif
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#define TMPSTACKSZ 16384
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#ifdef __powerpc64__
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#define GET_TOCBASE(r) \
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mfspr r, SPR_SPRG8
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#define TOC_RESTORE nop
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#define CMPI cmpdi
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#define CMPL cmpld
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#define LOAD ld
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#define LOADX ldarx
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#define STORE std
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#define STOREX stdcx.
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#define STU stdu
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#define CALLSIZE 48
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#define REDZONE 288
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#define THREAD_REG %r13
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#define ADDR(x) \
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.llong x
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#define WORD_SIZE 8
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#else
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#define GET_TOCBASE(r)
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#define TOC_RESTORE
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#define CMPI cmpwi
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#define CMPL cmplw
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#define LOAD lwz
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#define LOADX lwarx
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#define STOREX stwcx.
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#define STORE stw
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#define STU stwu
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#define CALLSIZE 8
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#define REDZONE 0
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#define THREAD_REG %r2
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#define ADDR(x) \
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.long x
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#define WORD_SIZE 4
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#endif
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#ifdef __powerpc64__
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/* Placate lld by creating a kboot stub. */
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.section ".text.kboot", "x", @progbits
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b __start
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#endif
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.text
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.globl btext
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btext:
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/*
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* This symbol is here for the benefit of kvm_mkdb, and is supposed to
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* mark the start of kernel text.
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*/
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.globl kernel_text
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kernel_text:
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/*
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* Startup entry. Note, this must be the first thing in the text segment!
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*/
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.text
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.globl __start
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__start:
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/*
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* Assumptions on the boot loader:
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* - System memory starts from physical address 0
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* - It's mapped by a single TLB1 entry
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* - TLB1 mapping is 1:1 pa to va
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* - Kernel is loaded at 64MB boundary
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* - All PID registers are set to the same value
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* - CPU is running in AS=0
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*
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* Registers contents provided by the loader(8):
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* r1 : stack pointer
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* r3 : metadata pointer
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*
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* We rearrange the TLB1 layout as follows:
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* - Find TLB1 entry we started in
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* - Make sure it's protected, invalidate other entries
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* - Create temp entry in the second AS (make sure it's not TLB[1])
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* - Switch to temp mapping
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* - Map 64MB of RAM in TLB1[1]
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* - Use AS=0, set EPN to VM_MIN_KERNEL_ADDRESS and RPN to kernel load address
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* - Switch to TLB1[1] mapping
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* - Invalidate temp mapping
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*
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* locore registers use:
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* r1 : stack pointer
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* r2 : trace pointer (AP only, for early diagnostics)
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* r3-r27 : scratch registers
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* r28 : temp TLB1 entry
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* r29 : initial TLB1 entry we started in
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* r30-r31 : arguments (metadata pointer)
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*/
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/*
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* Keep arguments in r30 & r31 for later use.
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*/
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mr %r30, %r3
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mr %r31, %r4
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/*
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* Initial cleanup
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*/
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li %r3, PSL_DE /* Keep debug exceptions for CodeWarrior. */
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#ifdef __powerpc64__
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oris %r3, %r3, PSL_CM@h
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#endif
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mtmsr %r3
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isync
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/*
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* Initial HIDs configuration
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*/
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1:
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mfpvr %r3
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rlwinm %r3, %r3, 16, 16, 31
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lis %r4, HID0_E500_DEFAULT_SET@h
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ori %r4, %r4, HID0_E500_DEFAULT_SET@l
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/* Check for e500mc and e5500 */
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cmpli 0, 0, %r3, FSL_E500mc
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bne 2f
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lis %r4, HID0_E500MC_DEFAULT_SET@h
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ori %r4, %r4, HID0_E500MC_DEFAULT_SET@l
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b 3f
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2:
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cmpli 0, 0, %r3, FSL_E5500
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bne 3f
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lis %r4, HID0_E5500_DEFAULT_SET@h
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ori %r4, %r4, HID0_E5500_DEFAULT_SET@l
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3:
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mtspr SPR_HID0, %r4
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isync
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/*
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* E500mc and E5500 do not have HID1 register, so skip HID1 setup on
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* this core.
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*/
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cmpli 0, 0, %r3, FSL_E500mc
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beq 1f
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cmpli 0, 0, %r3, FSL_E5500
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beq 1f
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cmpli 0, 0, %r3, FSL_E6500
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beq 1f
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lis %r3, HID1_E500_DEFAULT_SET@h
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ori %r3, %r3, HID1_E500_DEFAULT_SET@l
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mtspr SPR_HID1, %r3
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isync
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1:
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/* Invalidate all entries in TLB0 */
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li %r3, 0
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bl tlb_inval_all
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cmpwi %r30, 0
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beq done_mapping
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/*
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* Locate the TLB1 entry that maps this code
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*/
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bl 1f
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1: mflr %r3
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bl tlb1_find_current /* the entry found is returned in r29 */
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bl tlb1_inval_all_but_current
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/*
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* Create temporary mapping in AS=1 and switch to it
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*/
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bl tlb1_temp_mapping_as1
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mfmsr %r3
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ori %r3, %r3, (PSL_IS | PSL_DS)
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bl 2f
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2: mflr %r4
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addi %r4, %r4, (3f - 2b)
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mtspr SPR_SRR0, %r4
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mtspr SPR_SRR1, %r3
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rfi /* Switch context */
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/*
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* Invalidate initial entry
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*/
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3:
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mr %r3, %r29
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bl tlb1_inval_entry
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/*
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* Setup final mapping in TLB1[1] and switch to it
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*/
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/* Final kernel mapping, map in 64 MB of RAM */
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lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */
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li %r4, 0 /* Entry 0 */
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rlwimi %r3, %r4, 16, 10, 15
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mtspr SPR_MAS0, %r3
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isync
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li %r3, (TLB_SIZE_64M << MAS1_TSIZE_SHIFT)@l
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oris %r3, %r3, (MAS1_VALID | MAS1_IPROT)@h
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mtspr SPR_MAS1, %r3 /* note TS was not filled, so it's TS=0 */
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isync
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LOAD_ADDR(%r3, VM_MIN_KERNEL_ADDRESS)
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ori %r3, %r3, (_TLB_ENTRY_SHARED | MAS2_M)@l /* WIMGE = 0b00100 */
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mtspr SPR_MAS2, %r3
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isync
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/* Discover phys load address */
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bl 3f
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3: mflr %r4 /* Use current address */
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rlwinm %r4, %r4, 0, 0, 5 /* 64MB alignment mask */
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ori %r4, %r4, (MAS3_SX | MAS3_SW | MAS3_SR)@l
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mtspr SPR_MAS3, %r4 /* Set RPN and protection */
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isync
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li %r4, 0
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mtspr SPR_MAS7, %r4
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isync
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tlbwe
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isync
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msync
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/* Switch to the above TLB1[1] mapping */
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bl 4f
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4: mflr %r4
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#ifdef __powerpc64__
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clrldi %r4, %r4, 38
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clrrdi %r3, %r3, 12
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#else
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rlwinm %r4, %r4, 0, 6, 31 /* Current offset from kernel load address */
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rlwinm %r3, %r3, 0, 0, 19
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#endif
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add %r4, %r4, %r3 /* Convert to kernel virtual address */
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addi %r4, %r4, (5f - 4b)
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li %r3, PSL_DE /* Note AS=0 */
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#ifdef __powerpc64__
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oris %r3, %r3, PSL_CM@h
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#endif
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mtspr SPR_SRR0, %r4
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mtspr SPR_SRR1, %r3
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rfi
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/*
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* Invalidate temp mapping
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*/
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5:
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mr %r3, %r28
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bl tlb1_inval_entry
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done_mapping:
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#ifdef __powerpc64__
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/* Set up the TOC pointer */
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b 0f
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.align 3
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0: nop
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bl 1f
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.llong __tocbase + 0x8000 - .
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1: mflr %r2
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ld %r1,0(%r2)
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add %r2,%r1,%r2
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mtspr SPR_SPRG8, %r2
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nop
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/* Get load offset */
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ld %r31,-0x8000(%r2) /* First TOC entry is TOC base */
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subf %r31,%r31,%r2 /* Subtract from real TOC base to get base */
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/* Set up the stack pointer */
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bl 1f
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.llong tmpstack + TMPSTACKSZ - 96 - .
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1: mflr %r3
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ld %r1,0(%r3)
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add %r1,%r1,%r3
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/*
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* Relocate kernel
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*/
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bl 1f
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.llong _DYNAMIC-.
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1: mflr %r3
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ld %r4,0(%r3)
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add %r3,%r4,%r3
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mr %r4,%r31
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#else
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/*
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* Setup a temporary stack
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*/
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bl 1f
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.long tmpstack-.
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1: mflr %r1
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lwz %r2,0(%r1)
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add %r1,%r1,%r2
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addi %r1, %r1, (TMPSTACKSZ - 16)
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/*
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* Relocate kernel
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*/
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bl 1f
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.long _DYNAMIC-.
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.long _GLOBAL_OFFSET_TABLE_-.
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1: mflr %r5
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lwz %r3,0(%r5) /* _DYNAMIC in %r3 */
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add %r3,%r3,%r5
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lwz %r4,4(%r5) /* GOT pointer */
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add %r4,%r4,%r5
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lwz %r4,4(%r4) /* got[0] is _DYNAMIC link addr */
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subf %r4,%r4,%r3 /* subtract to calculate relocbase */
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#endif
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bl CNAME(elf_reloc_self)
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TOC_RESTORE
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/*
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* Initialise exception vector offsets
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*/
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bl CNAME(ivor_setup)
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TOC_RESTORE
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/*
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* Set up arguments and jump to system initialization code
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*/
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mr %r3, %r30
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mr %r4, %r31
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/* Prepare core */
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bl CNAME(booke_init)
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TOC_RESTORE
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/* Switch to thread0.td_kstack now */
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mr %r1, %r3
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li %r3, 0
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STORE %r3, 0(%r1)
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/* Machine independet part, does not return */
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bl CNAME(mi_startup)
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TOC_RESTORE
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/* NOT REACHED */
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5: b 5b
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#ifdef SMP
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/************************************************************************/
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/* AP Boot page */
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/************************************************************************/
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.text
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.globl __boot_page
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.align 12
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__boot_page:
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/*
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* The boot page is a special page of memory used during AP bringup.
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* Before the AP comes out of reset, the physical 4K page holding this
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* code is arranged to be mapped at 0xfffff000 by use of
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* platform-dependent registers.
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*
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* Alternatively, this page may be executed using an ePAPR-standardized
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* method -- writing to the address specified in "cpu-release-addr".
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*
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* In either case, execution begins at the last instruction of the
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* page, which is a branch back to the start of the page.
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*
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* The code in the page must do initial MMU setup and normalize the
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* TLBs for regular operation in the correct address space before
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* reading outside the page.
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*
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* This implementation accomplishes this by:
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* 1) Wiping TLB0 and all TLB1 entries but the one currently in use.
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* 2) Establishing a temporary 4K TLB1 mapping in AS=1, and switching
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* to it with rfi. This entry must NOT be in TLB1 slot 0.
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* (This is needed to give the code freedom to clean up AS=0.)
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* 3) Removing the initial TLB1 entry, leaving us with a single valid
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* TLB1 entry, NOT in slot 0.
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* 4) Installing an AS0 entry in TLB1 slot 0 mapping the 64MB kernel
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* segment at its final virtual address. A second rfi is done to
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* switch to the final address space. At this point we can finally
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* access the rest of the kernel segment safely.
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* 5) The temporary TLB1 AS=1 entry is removed, finally leaving us in
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* a consistent (but minimal) state.
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* 6) Set up TOC, stack, and pcpu registers.
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* 7) Now that we can finally call C code, call pmap_boostrap_ap(),
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* which finishes copying in the shared TLB1 entries.
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*
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* At this point, the MMU is fully set up, and we can proceed with
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* running the actual AP bootstrap code.
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*
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* Pieces of this code are also used for UP kernel, but in this case
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* the sections specific to boot page functionality are dropped by
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* the preprocessor.
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*/
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#ifdef __powerpc64__
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nop /* PPC64 alignment word. 64-bit target. */
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#endif
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bl 1f /* 32-bit target. */
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.globl bp_trace
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bp_trace:
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ADDR(0) /* Trace pointer (%r31). */
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.globl bp_kernload
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bp_kernload:
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.llong 0 /* Kern phys. load address. */
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.globl bp_virtaddr
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bp_virtaddr:
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ADDR(0) /* Virt. address of __boot_page. */
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/*
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* Initial configuration
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*/
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1:
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mflr %r31 /* r31 hold the address of bp_trace */
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/* Set HIDs */
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mfpvr %r3
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rlwinm %r3, %r3, 16, 16, 31
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/* HID0 for E500 is default */
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lis %r4, HID0_E500_DEFAULT_SET@h
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ori %r4, %r4, HID0_E500_DEFAULT_SET@l
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cmpli 0, 0, %r3, FSL_E500mc
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bne 2f
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lis %r4, HID0_E500MC_DEFAULT_SET@h
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ori %r4, %r4, HID0_E500MC_DEFAULT_SET@l
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b 3f
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2:
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cmpli 0, 0, %r3, FSL_E5500
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bne 3f
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lis %r4, HID0_E5500_DEFAULT_SET@h
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ori %r4, %r4, HID0_E5500_DEFAULT_SET@l
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3:
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mtspr SPR_HID0, %r4
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isync
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/* Enable branch prediction */
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li %r3, BUCSR_BPEN
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mtspr SPR_BUCSR, %r3
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isync
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/* Invalidate all entries in TLB0 */
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li %r3, 0
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bl tlb_inval_all
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/*
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* Find TLB1 entry which is translating us now
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*/
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bl 2f
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2: mflr %r3
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bl tlb1_find_current /* the entry number found is in r29 */
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bl tlb1_inval_all_but_current
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/*
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* Create temporary translation in AS=1 and switch to it
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*/
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bl tlb1_temp_mapping_as1
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mfmsr %r3
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ori %r3, %r3, (PSL_IS | PSL_DS)
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#ifdef __powerpc64__
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oris %r3, %r3, PSL_CM@h /* Ensure we're in 64-bit after RFI */
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#endif
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bl 3f
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3: mflr %r4
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addi %r4, %r4, (4f - 3b)
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mtspr SPR_SRR0, %r4
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mtspr SPR_SRR1, %r3
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rfi /* Switch context */
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/*
|
|
* Invalidate initial entry
|
|
*/
|
|
4:
|
|
mr %r3, %r29
|
|
bl tlb1_inval_entry
|
|
|
|
/*
|
|
* Setup final mapping in TLB1[0] and switch to it
|
|
*/
|
|
/* Final kernel mapping, map in 64 MB of RAM */
|
|
lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */
|
|
li %r4, 0 /* Entry 0 */
|
|
rlwimi %r3, %r4, 16, 4, 15
|
|
mtspr SPR_MAS0, %r3
|
|
isync
|
|
|
|
li %r3, (TLB_SIZE_64M << MAS1_TSIZE_SHIFT)@l
|
|
oris %r3, %r3, (MAS1_VALID | MAS1_IPROT)@h
|
|
mtspr SPR_MAS1, %r3 /* note TS was not filled, so it's TS=0 */
|
|
isync
|
|
|
|
LOAD_ADDR(%r3, VM_MIN_KERNEL_ADDRESS)
|
|
ori %r3, %r3, (_TLB_ENTRY_SHARED | MAS2_M)@l /* WIMGE = 0b00100 */
|
|
mtspr SPR_MAS2, %r3
|
|
isync
|
|
|
|
/* Retrieve kernel load [physical] address from bp_kernload */
|
|
5:
|
|
mflr %r3
|
|
#ifdef __powerpc64__
|
|
clrrdi %r3, %r3, PAGE_SHIFT /* trunc_page(%r3) */
|
|
#else
|
|
clrrwi %r3, %r3, PAGE_SHIFT /* trunc_page(%r3) */
|
|
#endif
|
|
/* Load lower half of the kernel loadaddr. */
|
|
lwz %r4, (bp_kernload - __boot_page + 4)(%r3)
|
|
LOAD %r5, (bp_virtaddr - __boot_page)(%r3)
|
|
|
|
/* Set RPN and protection */
|
|
ori %r4, %r4, (MAS3_SX | MAS3_SW | MAS3_SR)@l
|
|
mtspr SPR_MAS3, %r4
|
|
isync
|
|
lwz %r4, (bp_kernload - __boot_page)(%r3)
|
|
mtspr SPR_MAS7, %r4
|
|
isync
|
|
tlbwe
|
|
isync
|
|
msync
|
|
|
|
/* Switch to the final mapping */
|
|
bl 6f
|
|
6: mflr %r3
|
|
rlwinm %r3, %r3, 0, 0xfff /* Offset from boot page start */
|
|
add %r3, %r3, %r5 /* Make this a virtual address */
|
|
addi %r3, %r3, (7f - 6b) /* And figure out return address. */
|
|
#ifdef __powerpc64__
|
|
lis %r4, PSL_CM@h /* Note AS=0 */
|
|
#else
|
|
li %r4, 0 /* Note AS=0 */
|
|
#endif
|
|
mtspr SPR_SRR0, %r3
|
|
mtspr SPR_SRR1, %r4
|
|
rfi
|
|
7:
|
|
|
|
/*
|
|
* At this point we're running at virtual addresses VM_MIN_KERNEL_ADDRESS and
|
|
* beyond so it's allowed to directly access all locations the kernel was linked
|
|
* against.
|
|
*/
|
|
|
|
/*
|
|
* Invalidate temp mapping
|
|
*/
|
|
mr %r3, %r28
|
|
bl tlb1_inval_entry
|
|
|
|
#ifdef __powerpc64__
|
|
/* Set up the TOC pointer */
|
|
b 0f
|
|
.align 3
|
|
0: nop
|
|
bl 1f
|
|
.llong __tocbase + 0x8000 - .
|
|
1: mflr %r2
|
|
ld %r1,0(%r2)
|
|
add %r2,%r1,%r2
|
|
mtspr SPR_SPRG8, %r2
|
|
|
|
/* Set up the stack pointer */
|
|
addis %r1,%r2,TOC_REF(tmpstack)@ha
|
|
ld %r1,TOC_REF(tmpstack)@l(%r1)
|
|
addi %r1,%r1,TMPSTACKSZ-96
|
|
#else
|
|
/*
|
|
* Setup a temporary stack
|
|
*/
|
|
bl 1f
|
|
.long tmpstack-.
|
|
1: mflr %r1
|
|
lwz %r2,0(%r1)
|
|
add %r1,%r1,%r2
|
|
stw %r1, 0(%r1)
|
|
addi %r1, %r1, (TMPSTACKSZ - 16)
|
|
#endif
|
|
|
|
/*
|
|
* Initialise exception vector offsets
|
|
*/
|
|
bl CNAME(ivor_setup)
|
|
TOC_RESTORE
|
|
|
|
/*
|
|
* Assign our pcpu instance
|
|
*/
|
|
bl 1f
|
|
.long ap_pcpu-.
|
|
1: mflr %r4
|
|
lwz %r3, 0(%r4)
|
|
add %r3, %r3, %r4
|
|
LOAD %r3, 0(%r3)
|
|
mtsprg0 %r3
|
|
|
|
bl CNAME(pmap_bootstrap_ap)
|
|
TOC_RESTORE
|
|
|
|
bl CNAME(cpudep_ap_bootstrap)
|
|
TOC_RESTORE
|
|
/* Switch to the idle thread's kstack */
|
|
mr %r1, %r3
|
|
|
|
bl CNAME(machdep_ap_bootstrap)
|
|
TOC_RESTORE
|
|
|
|
/* NOT REACHED */
|
|
6: b 6b
|
|
#endif /* SMP */
|
|
|
|
#if defined (BOOKE_E500)
|
|
/*
|
|
* Invalidate all entries in the given TLB.
|
|
*
|
|
* r3 TLBSEL
|
|
*/
|
|
tlb_inval_all:
|
|
rlwinm %r3, %r3, 3, (1 << 3) /* TLBSEL */
|
|
ori %r3, %r3, (1 << 2) /* INVALL */
|
|
tlbivax 0, %r3
|
|
isync
|
|
msync
|
|
|
|
tlbsync
|
|
msync
|
|
blr
|
|
|
|
/*
|
|
* expects address to look up in r3, returns entry number in r29
|
|
*
|
|
* FIXME: the hidden assumption is we are now running in AS=0, but we should
|
|
* retrieve actual AS from MSR[IS|DS] and put it in MAS6[SAS]
|
|
*/
|
|
tlb1_find_current:
|
|
mfspr %r17, SPR_PID0
|
|
slwi %r17, %r17, MAS6_SPID0_SHIFT
|
|
mtspr SPR_MAS6, %r17
|
|
isync
|
|
tlbsx 0, %r3
|
|
mfspr %r17, SPR_MAS0
|
|
rlwinm %r29, %r17, 16, 26, 31 /* MAS0[ESEL] -> r29 */
|
|
|
|
/* Make sure we have IPROT set on the entry */
|
|
mfspr %r17, SPR_MAS1
|
|
oris %r17, %r17, MAS1_IPROT@h
|
|
mtspr SPR_MAS1, %r17
|
|
isync
|
|
tlbwe
|
|
isync
|
|
msync
|
|
blr
|
|
|
|
/*
|
|
* Invalidates a single entry in TLB1.
|
|
*
|
|
* r3 ESEL
|
|
* r4-r5 scratched
|
|
*/
|
|
tlb1_inval_entry:
|
|
lis %r4, MAS0_TLBSEL1@h /* Select TLB1 */
|
|
rlwimi %r4, %r3, 16, 10, 15 /* Select our entry */
|
|
mtspr SPR_MAS0, %r4
|
|
isync
|
|
tlbre
|
|
li %r5, 0 /* MAS1[V] = 0 */
|
|
mtspr SPR_MAS1, %r5
|
|
isync
|
|
tlbwe
|
|
isync
|
|
msync
|
|
blr
|
|
|
|
/*
|
|
* r29 current entry number
|
|
* r28 returned temp entry
|
|
* r3-r5 scratched
|
|
*/
|
|
tlb1_temp_mapping_as1:
|
|
/* Read our current translation */
|
|
lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */
|
|
rlwimi %r3, %r29, 16, 10, 15 /* Select our current entry */
|
|
mtspr SPR_MAS0, %r3
|
|
isync
|
|
tlbre
|
|
|
|
/*
|
|
* Prepare and write temp entry
|
|
*
|
|
* FIXME this is not robust against overflow i.e. when the current
|
|
* entry is the last in TLB1
|
|
*/
|
|
lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */
|
|
addi %r28, %r29, 1 /* Use next entry. */
|
|
rlwimi %r3, %r28, 16, 10, 15 /* Select temp entry */
|
|
mtspr SPR_MAS0, %r3
|
|
isync
|
|
mfspr %r5, SPR_MAS1
|
|
li %r4, 1 /* AS=1 */
|
|
rlwimi %r5, %r4, 12, 19, 19
|
|
li %r4, 0 /* Global mapping, TID=0 */
|
|
rlwimi %r5, %r4, 16, 8, 15
|
|
oris %r5, %r5, (MAS1_VALID | MAS1_IPROT)@h
|
|
mtspr SPR_MAS1, %r5
|
|
isync
|
|
mflr %r3
|
|
li %r4, 0
|
|
mtspr SPR_MAS7, %r4
|
|
mtlr %r3
|
|
isync
|
|
tlbwe
|
|
isync
|
|
msync
|
|
blr
|
|
|
|
/*
|
|
* Loops over TLB1, invalidates all entries skipping the one which currently
|
|
* maps this code.
|
|
*
|
|
* r29 current entry
|
|
* r3-r5 scratched
|
|
*/
|
|
tlb1_inval_all_but_current:
|
|
mfspr %r3, SPR_TLB1CFG /* Get number of entries */
|
|
andi. %r3, %r3, TLBCFG_NENTRY_MASK@l
|
|
li %r4, 0 /* Start from Entry 0 */
|
|
1: lis %r5, MAS0_TLBSEL1@h
|
|
rlwimi %r5, %r4, 16, 10, 15
|
|
mtspr SPR_MAS0, %r5
|
|
isync
|
|
tlbre
|
|
mfspr %r5, SPR_MAS1
|
|
cmpw %r4, %r29 /* our current entry? */
|
|
beq 2f
|
|
rlwinm %r5, %r5, 0, 2, 31 /* clear VALID and IPROT bits */
|
|
mtspr SPR_MAS1, %r5
|
|
isync
|
|
tlbwe
|
|
isync
|
|
msync
|
|
2: addi %r4, %r4, 1
|
|
cmpw %r4, %r3 /* Check if this is the last entry */
|
|
bne 1b
|
|
blr
|
|
#endif
|
|
|
|
#ifdef SMP
|
|
.globl __boot_tlb1
|
|
/*
|
|
* The __boot_tlb1 table is used to hold BSP TLB1 entries
|
|
* marked with _TLB_ENTRY_SHARED flag during AP bootstrap.
|
|
* The BSP fills in the table in tlb_ap_prep() function. Next,
|
|
* AP loads its contents to TLB1 hardware in pmap_bootstrap_ap().
|
|
*/
|
|
__boot_tlb1:
|
|
.space TLB1_MAX_ENTRIES * TLB_ENTRY_SIZE
|
|
|
|
__boot_page_padding:
|
|
/*
|
|
* Boot page needs to be exactly 4K, with the last word of this page
|
|
* acting as the reset vector, so we need to stuff the remainder.
|
|
* Upon release from holdoff CPU fetches the last word of the boot
|
|
* page.
|
|
*/
|
|
.space 4092 - (__boot_page_padding - __boot_page)
|
|
b __boot_page
|
|
/*
|
|
* This is the end of the boot page.
|
|
* During AP startup, the previous instruction is at 0xfffffffc
|
|
* virtual (i.e. the reset vector.)
|
|
*/
|
|
#endif /* SMP */
|
|
|
|
/************************************************************************/
|
|
/* locore subroutines */
|
|
/************************************************************************/
|
|
|
|
/*
|
|
* Cache disable/enable/inval sequences according
|
|
* to section 2.16 of E500CORE RM.
|
|
*/
|
|
ENTRY(dcache_inval)
|
|
/* Invalidate d-cache */
|
|
mfspr %r3, SPR_L1CSR0
|
|
ori %r3, %r3, (L1CSR0_DCFI | L1CSR0_DCLFR)@l
|
|
msync
|
|
isync
|
|
mtspr SPR_L1CSR0, %r3
|
|
isync
|
|
1: mfspr %r3, SPR_L1CSR0
|
|
andi. %r3, %r3, L1CSR0_DCFI
|
|
bne 1b
|
|
blr
|
|
|
|
ENTRY(dcache_disable)
|
|
/* Disable d-cache */
|
|
mfspr %r3, SPR_L1CSR0
|
|
li %r4, L1CSR0_DCE@l
|
|
not %r4, %r4
|
|
and %r3, %r3, %r4
|
|
msync
|
|
isync
|
|
mtspr SPR_L1CSR0, %r3
|
|
isync
|
|
blr
|
|
|
|
ENTRY(dcache_enable)
|
|
/* Enable d-cache */
|
|
mfspr %r3, SPR_L1CSR0
|
|
oris %r3, %r3, (L1CSR0_DCPE | L1CSR0_DCE)@h
|
|
ori %r3, %r3, (L1CSR0_DCPE | L1CSR0_DCE)@l
|
|
msync
|
|
isync
|
|
mtspr SPR_L1CSR0, %r3
|
|
isync
|
|
blr
|
|
|
|
ENTRY(icache_inval)
|
|
/* Invalidate i-cache */
|
|
mfspr %r3, SPR_L1CSR1
|
|
ori %r3, %r3, (L1CSR1_ICFI | L1CSR1_ICLFR)@l
|
|
isync
|
|
mtspr SPR_L1CSR1, %r3
|
|
isync
|
|
1: mfspr %r3, SPR_L1CSR1
|
|
andi. %r3, %r3, L1CSR1_ICFI
|
|
bne 1b
|
|
blr
|
|
|
|
ENTRY(icache_disable)
|
|
/* Disable i-cache */
|
|
mfspr %r3, SPR_L1CSR1
|
|
li %r4, L1CSR1_ICE@l
|
|
not %r4, %r4
|
|
and %r3, %r3, %r4
|
|
isync
|
|
mtspr SPR_L1CSR1, %r3
|
|
isync
|
|
blr
|
|
|
|
ENTRY(icache_enable)
|
|
/* Enable i-cache */
|
|
mfspr %r3, SPR_L1CSR1
|
|
oris %r3, %r3, (L1CSR1_ICPE | L1CSR1_ICE)@h
|
|
ori %r3, %r3, (L1CSR1_ICPE | L1CSR1_ICE)@l
|
|
isync
|
|
mtspr SPR_L1CSR1, %r3
|
|
isync
|
|
blr
|
|
|
|
/*
|
|
* L2 cache disable/enable/inval sequences for E500mc.
|
|
*/
|
|
|
|
ENTRY(l2cache_inval)
|
|
mfspr %r3, SPR_L2CSR0
|
|
oris %r3, %r3, (L2CSR0_L2FI | L2CSR0_L2LFC)@h
|
|
ori %r3, %r3, (L2CSR0_L2FI | L2CSR0_L2LFC)@l
|
|
isync
|
|
mtspr SPR_L2CSR0, %r3
|
|
isync
|
|
1: mfspr %r3, SPR_L2CSR0
|
|
andis. %r3, %r3, L2CSR0_L2FI@h
|
|
bne 1b
|
|
blr
|
|
|
|
ENTRY(l2cache_enable)
|
|
mfspr %r3, SPR_L2CSR0
|
|
oris %r3, %r3, (L2CSR0_L2E | L2CSR0_L2PE)@h
|
|
isync
|
|
mtspr SPR_L2CSR0, %r3
|
|
isync
|
|
blr
|
|
|
|
/*
|
|
* Branch predictor setup.
|
|
*/
|
|
ENTRY(bpred_enable)
|
|
mfspr %r3, SPR_BUCSR
|
|
ori %r3, %r3, BUCSR_BBFI
|
|
isync
|
|
mtspr SPR_BUCSR, %r3
|
|
isync
|
|
ori %r3, %r3, BUCSR_BPEN
|
|
isync
|
|
mtspr SPR_BUCSR, %r3
|
|
isync
|
|
blr
|
|
|
|
/*
|
|
* XXX: This should be moved to a shared AIM/booke asm file, if one ever is
|
|
* created.
|
|
*/
|
|
ENTRY(get_spr)
|
|
/* Note: The spr number is patched at runtime */
|
|
mfspr %r3, 0
|
|
blr
|
|
|
|
/************************************************************************/
|
|
/* Data section */
|
|
/************************************************************************/
|
|
.data
|
|
.align 3
|
|
GLOBAL(__startkernel)
|
|
ADDR(begin)
|
|
GLOBAL(__endkernel)
|
|
ADDR(end)
|
|
.align 4
|
|
tmpstack:
|
|
.space TMPSTACKSZ
|
|
tmpstackbound:
|
|
.space 10240 /* XXX: this really should not be necessary */
|
|
#ifdef __powerpc64__
|
|
TOC_ENTRY(tmpstack)
|
|
#ifdef SMP
|
|
TOC_ENTRY(bp_kernload)
|
|
#endif
|
|
#endif
|
|
|
|
/*
|
|
* Compiled KERNBASE locations
|
|
*/
|
|
.globl kernbase
|
|
.set kernbase, KERNBASE
|
|
|
|
#include <powerpc/booke/trap_subr.S>
|