448 lines
13 KiB
C
448 lines
13 KiB
C
/*-
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* Copyright (C) 2012 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __NVME_PRIVATE_H__
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#define __NVME_PRIVATE_H__
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <sys/systm.h>
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#include <vm/uma.h>
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#include <machine/bus.h>
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#include "nvme.h"
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#define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev))
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MALLOC_DECLARE(M_NVME);
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#define CHATHAM2
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#ifdef CHATHAM2
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#define CHATHAM_PCI_ID 0x20118086
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#define CHATHAM_CONTROL_BAR 0
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#endif
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#define IDT32_PCI_ID 0x80d0111d /* 32 channel board */
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#define IDT8_PCI_ID 0x80d2111d /* 8 channel board */
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#define NVME_MAX_PRP_LIST_ENTRIES (32)
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/*
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* For commands requiring more than 2 PRP entries, one PRP will be
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* embedded in the command (prp1), and the rest of the PRP entries
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* will be in a list pointed to by the command (prp2). This means
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* that real max number of PRP entries we support is 32+1, which
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* results in a max xfer size of 32*PAGE_SIZE.
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*/
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#define NVME_MAX_XFER_SIZE NVME_MAX_PRP_LIST_ENTRIES * PAGE_SIZE
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#define NVME_ADMIN_TRACKERS (16)
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#define NVME_ADMIN_ENTRIES (128)
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/* min and max are defined in admin queue attributes section of spec */
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#define NVME_MIN_ADMIN_ENTRIES (2)
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#define NVME_MAX_ADMIN_ENTRIES (4096)
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/*
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* NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion
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* queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we
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* will allow outstanding on an I/O qpair at any time. The only advantage in
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* having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping
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* the contents of the submission and completion queues, it will show a longer
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* history of data.
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*/
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#define NVME_IO_ENTRIES (256)
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#define NVME_IO_TRACKERS (128)
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#define NVME_MIN_IO_TRACKERS (16)
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#define NVME_MAX_IO_TRACKERS (1024)
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/*
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* NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES
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* for each controller.
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*/
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#define NVME_INT_COAL_TIME (0) /* disabled */
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#define NVME_INT_COAL_THRESHOLD (0) /* 0-based */
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#define NVME_MAX_NAMESPACES (16)
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#define NVME_MAX_CONSUMERS (2)
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#define NVME_MAX_ASYNC_EVENTS (8)
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#define NVME_TIMEOUT_IN_SEC (30)
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#ifndef CACHE_LINE_SIZE
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#define CACHE_LINE_SIZE (64)
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#endif
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extern uma_zone_t nvme_request_zone;
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struct nvme_request {
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struct nvme_command cmd;
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void *payload;
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uint32_t payload_size;
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uint32_t timeout;
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struct uio *uio;
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nvme_cb_fn_t cb_fn;
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void *cb_arg;
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STAILQ_ENTRY(nvme_request) stailq;
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};
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struct nvme_async_event_request {
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struct nvme_controller *ctrlr;
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struct nvme_request *req;
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};
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struct nvme_tracker {
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SLIST_ENTRY(nvme_tracker) slist;
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struct nvme_request *req;
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struct nvme_qpair *qpair;
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struct callout timer;
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bus_dmamap_t payload_dma_map;
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uint16_t cid;
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uint64_t prp[NVME_MAX_PRP_LIST_ENTRIES];
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bus_addr_t prp_bus_addr;
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bus_dmamap_t prp_dma_map;
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};
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struct nvme_qpair {
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struct nvme_controller *ctrlr;
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uint32_t id;
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uint32_t phase;
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uint16_t vector;
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int rid;
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struct resource *res;
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void *tag;
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uint32_t max_xfer_size;
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uint32_t num_entries;
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uint32_t num_trackers;
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uint32_t sq_tdbl_off;
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uint32_t cq_hdbl_off;
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uint32_t sq_head;
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uint32_t sq_tail;
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uint32_t cq_head;
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int64_t num_cmds;
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int64_t num_intr_handler_calls;
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struct nvme_command *cmd;
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struct nvme_completion *cpl;
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bus_dma_tag_t dma_tag;
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bus_dmamap_t cmd_dma_map;
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uint64_t cmd_bus_addr;
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bus_dmamap_t cpl_dma_map;
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uint64_t cpl_bus_addr;
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SLIST_HEAD(, nvme_tracker) free_tr;
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STAILQ_HEAD(, nvme_request) queued_req;
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struct nvme_tracker **act_tr;
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struct mtx lock __aligned(CACHE_LINE_SIZE);
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} __aligned(CACHE_LINE_SIZE);
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struct nvme_namespace {
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struct nvme_controller *ctrlr;
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struct nvme_namespace_data data;
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uint16_t id;
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uint16_t flags;
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struct cdev *cdev;
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void *cons_cookie[NVME_MAX_CONSUMERS];
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};
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/*
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* One of these per allocated PCI device.
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*/
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struct nvme_controller {
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device_t dev;
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uint32_t ready_timeout_in_ms;
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bus_space_tag_t bus_tag;
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bus_space_handle_t bus_handle;
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int resource_id;
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struct resource *resource;
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/*
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* The NVMe spec allows for the MSI-X table to be placed in BAR 4/5,
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* separate from the control registers which are in BAR 0/1. These
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* members track the mapping of BAR 4/5 for that reason.
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*/
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int bar4_resource_id;
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struct resource *bar4_resource;
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#ifdef CHATHAM2
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bus_space_tag_t chatham_bus_tag;
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bus_space_handle_t chatham_bus_handle;
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int chatham_resource_id;
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struct resource *chatham_resource;
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#endif
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uint32_t msix_enabled;
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uint32_t force_intx;
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uint32_t num_io_queues;
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boolean_t per_cpu_io_queues;
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/* Fields for tracking progress during controller initialization. */
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struct intr_config_hook config_hook;
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uint32_t ns_identified;
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uint32_t queues_created;
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/* For shared legacy interrupt. */
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int rid;
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struct resource *res;
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void *tag;
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bus_dma_tag_t hw_desc_tag;
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bus_dmamap_t hw_desc_map;
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/** maximum i/o size in bytes */
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uint32_t max_xfer_size;
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/** interrupt coalescing time period (in microseconds) */
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uint32_t int_coal_time;
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/** interrupt coalescing threshold */
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uint32_t int_coal_threshold;
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struct nvme_qpair adminq;
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struct nvme_qpair *ioq;
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struct nvme_registers *regs;
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struct nvme_controller_data cdata;
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struct nvme_namespace ns[NVME_MAX_NAMESPACES];
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struct cdev *cdev;
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boolean_t is_started;
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uint32_t num_aers;
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struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS];
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void *cons_cookie[NVME_MAX_CONSUMERS];
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#ifdef CHATHAM2
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uint64_t chatham_size;
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uint64_t chatham_lbas;
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#endif
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};
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#define nvme_mmio_offsetof(reg) \
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offsetof(struct nvme_registers, reg)
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#define nvme_mmio_read_4(sc, reg) \
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bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \
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nvme_mmio_offsetof(reg))
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#define nvme_mmio_write_4(sc, reg, val) \
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bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
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nvme_mmio_offsetof(reg), val)
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#define nvme_mmio_write_8(sc, reg, val) \
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do { \
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bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
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nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \
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bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \
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nvme_mmio_offsetof(reg)+4, \
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(val & 0xFFFFFFFF00000000UL) >> 32); \
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} while (0);
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#ifdef CHATHAM2
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#define chatham_read_4(softc, reg) \
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bus_space_read_4((softc)->chatham_bus_tag, \
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(softc)->chatham_bus_handle, reg)
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#define chatham_write_8(sc, reg, val) \
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do { \
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bus_space_write_4((sc)->chatham_bus_tag, \
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(sc)->chatham_bus_handle, reg, val & 0xffffffff); \
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bus_space_write_4((sc)->chatham_bus_tag, \
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(sc)->chatham_bus_handle, reg+4, \
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(val & 0xFFFFFFFF00000000UL) >> 32); \
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} while (0);
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#endif /* CHATHAM2 */
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#if __FreeBSD_version < 800054
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#define wmb() __asm volatile("sfence" ::: "memory")
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#define mb() __asm volatile("mfence" ::: "memory")
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#endif
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void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg);
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void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr,
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void *payload,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr,
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uint16_t nsid, void *payload,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr,
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uint32_t microseconds,
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uint32_t threshold,
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nvme_cb_fn_t cb_fn,
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void *cb_arg);
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void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr,
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uint32_t nsid,
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struct nvme_health_information_page *payload,
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nvme_cb_fn_t cb_fn,
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void *cb_arg);
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void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr,
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struct nvme_qpair *io_que, uint16_t vector,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr,
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struct nvme_qpair *io_que,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr,
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struct nvme_qpair *io_que,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr,
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struct nvme_qpair *io_que,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr,
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uint32_t num_queues, nvme_cb_fn_t cb_fn,
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void *cb_arg);
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void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr,
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union nvme_critical_warning_state state,
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nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid,
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uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg);
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void nvme_payload_map(void *arg, bus_dma_segment_t *seg, int nseg,
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int error);
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void nvme_payload_map_uio(void *arg, bus_dma_segment_t *seg, int nseg,
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bus_size_t mapsize, int error);
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int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev);
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void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev);
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int nvme_ctrlr_reset(struct nvme_controller *ctrlr);
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/* ctrlr defined as void * to allow use with config_intrhook. */
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void nvme_ctrlr_start(void *ctrlr_arg);
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void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr,
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struct nvme_request *req);
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void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr,
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struct nvme_request *req);
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void nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id,
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uint16_t vector, uint32_t num_entries,
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uint32_t num_trackers, uint32_t max_xfer_size,
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struct nvme_controller *ctrlr);
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void nvme_qpair_submit_cmd(struct nvme_qpair *qpair,
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struct nvme_tracker *tr);
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void nvme_qpair_process_completions(struct nvme_qpair *qpair);
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void nvme_qpair_submit_request(struct nvme_qpair *qpair,
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struct nvme_request *req);
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void nvme_qpair_manual_abort_request(struct nvme_qpair *qpair,
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struct nvme_request *req, uint32_t sct,
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uint32_t sc, boolean_t print_on_error);
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void nvme_admin_qpair_destroy(struct nvme_qpair *qpair);
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void nvme_io_qpair_destroy(struct nvme_qpair *qpair);
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int nvme_ns_construct(struct nvme_namespace *ns, uint16_t id,
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struct nvme_controller *ctrlr);
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int nvme_ns_physio(struct cdev *dev, struct uio *uio, int ioflag);
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void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr);
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void nvme_dump_command(struct nvme_command *cmd);
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void nvme_dump_completion(struct nvme_completion *cpl);
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static __inline void
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nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error)
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{
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uint64_t *bus_addr = (uint64_t *)arg;
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*bus_addr = seg[0].ds_addr;
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}
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static __inline struct nvme_request *
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nvme_allocate_request(void *payload, uint32_t payload_size, nvme_cb_fn_t cb_fn,
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void *cb_arg)
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{
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struct nvme_request *req;
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req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO);
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if (req == NULL)
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return (NULL);
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req->payload = payload;
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req->payload_size = payload_size;
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req->cb_fn = cb_fn;
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req->cb_arg = cb_arg;
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req->timeout = NVME_TIMEOUT_IN_SEC;
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return (req);
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}
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static __inline struct nvme_request *
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nvme_allocate_request_uio(struct uio *uio, nvme_cb_fn_t cb_fn, void *cb_arg)
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{
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struct nvme_request *req;
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req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO);
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if (req == NULL)
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return (NULL);
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req->uio = uio;
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req->cb_fn = cb_fn;
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req->cb_arg = cb_arg;
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req->timeout = NVME_TIMEOUT_IN_SEC;
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return (req);
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}
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#define nvme_free_request(req) uma_zfree(nvme_request_zone, req)
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void nvme_notify_async_consumers(struct nvme_controller *ctrlr,
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const struct nvme_completion *async_cpl);
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#endif /* __NVME_PRIVATE_H__ */
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