96 lines
3.2 KiB
Groff
96 lines
3.2 KiB
Groff
.\"
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.\" Copyright (c) 2013 Thomas Skibo
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. The name of the author may not be used to endorse or promote products
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.\" derived from this software without specific prior written permission.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd February 28, 2013
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.Dt DEVCFG 4
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.Os
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.Sh NAME
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.Nm devcfg
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.Nd Zynq PL device config interface
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.Sh SYNOPSIS
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.Cd device devcfg
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.Sh DESCRIPTION
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The special file
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.Pa /dev/devcfg
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can be used to configure the PL (FPGA) section of the Xilinx Zynq-7000.
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.Pp
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On the first write to the character device at file offset 0, the
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.Nm
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driver
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asserts the top-level PL reset signals, disables the PS-PL level shifters,
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and clears the PL configuration.
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Write data is sent to the PCAP (processor configuration access port).
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When the PL asserts the DONE signal, the devcfg driver will enable the level
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shifters and release the top-level PL reset signals.
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.Pp
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The PL (FPGA) can be configured by writing the bitstream to the character
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device like this:
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.Bd -literal -offset indent
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cat design.bit.bin > /dev/devcfg
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.Ed
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.Pp
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The file should not be confused with the .bit file output by the FPGA
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design tools.
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It is the binary form of the configuration bitstream.
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The Xilinx
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.Ic promgen
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tool can do the conversion:
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.Bd -literal -offset indent
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promgen -b -w -p bin -data_width 32 -u 0 design.bit -o design.bit.bin
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.Ed
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.Sh SYSCTL VARIABLES
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The
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.Nm
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driver provides the following
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.Xr sysctl 8
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variables:
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.Bl -tag -width 4n
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.It Va hw.fpga.pl_done
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.Pp
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This variable always reflects the status of the PL's DONE signal.
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A 1 means the PL section has been properly programmed.
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.It Va hw.fpga.en_level_shifters
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.Pp
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This variable controls if the PS-PL level shifters are enabled after the
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PL section has been reconfigured.
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This variable is 1 by default but setting it to 0 allows the PL section to be
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programmed with configurations that do not interface to the PS section of the
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part.
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Changing this value has no effect on the level shifters until the next device
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reconfiguration.
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.El
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.Sh FILES
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.Bl -tag -width 12n
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.It Pa /dev/devcfg
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Character device for the
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.Nm
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driver.
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.El
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.Sh SEE ALSO
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Zynq-7000 SoC Technical Reference Manual (Xilinx doc UG585)
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.Sh AUTHORS
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.An Thomas Skibo
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