375307d411
I couldn't think of a way to maintain the hardware TXQ locks _and_ layer on top of that per-TXQ software queuing and any other kind of fine-grained locks (eg per-TID, or per-node locks.) So for now, to facilitate some further code refactoring and development as part of the final push to get software queue ps-poll and u-apsd handling into this driver, just do away with them entirely. I may eventually bring them back at some point, when it looks slightly more architectually cleaner to do so. But as it stands at the present, it's not really buying us much: * in order to properly serialise things and not get bitten by scheduling and locking interactions with things higher up in the stack, we need to wrap the whole TX path in a long held lock. Otherwise we can end up being pre-empted during frame handling, resulting in some out of order frame handling between sequence number allocation and encryption handling (ie, the seqno and the CCMP IV get out of sequence); * .. so whilst that's the case, holding the lock for that long means that we're acquiring and releasing the TXQ lock _inside_ that context; * And we also acquire it per-frame during frame completion, but we currently can't hold the lock for the duration of the TX completion as we need to call net80211 layer things with the locks _unheld_ to avoid LOR. * .. the other places were grab that lock are reset/flush, which don't happen often. My eventual aim is to change the TX path so all rejected frame transmissions and all frame completions result in any ieee80211_free_node() calls to occur outside of the TX lock; then I can cut back on the amount of locking that goes on here. There may be some LORs that occur when ieee80211_free_node() is called when the TX queue path fails; I'll begin to address these in follow-up commits.
692 lines
18 KiB
C
692 lines
18 KiB
C
/*-
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* Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Driver for the Atheros Wireless LAN controller.
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*
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* This software is derived from work of Atsushi Onoe; his contribution
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* is greatly appreciated.
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*/
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#include "opt_inet.h"
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#include "opt_ath.h"
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/*
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* This is needed for register operations which are performed
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* by the driver - eg, calls to ath_hal_gettsf32().
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*
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* It's also required for any AH_DEBUG checks in here, eg the
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* module dependencies.
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*/
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#include "opt_ah.h"
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#include "opt_wlan.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/sysctl.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/sockio.h>
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#include <sys/errno.h>
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#include <sys/callout.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/kthread.h>
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#include <sys/taskqueue.h>
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#include <sys/priv.h>
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#include <sys/module.h>
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#include <sys/ktr.h>
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#include <sys/smp.h> /* for mp_ncpus */
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#include <machine/bus.h>
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#include <net/if.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_types.h>
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#include <net/if_arp.h>
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#include <net/ethernet.h>
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#include <net/if_llc.h>
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#include <net80211/ieee80211_var.h>
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#include <net80211/ieee80211_regdomain.h>
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#ifdef IEEE80211_SUPPORT_SUPERG
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#include <net80211/ieee80211_superg.h>
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#endif
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#ifdef IEEE80211_SUPPORT_TDMA
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#include <net80211/ieee80211_tdma.h>
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#endif
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#include <net/bpf.h>
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#ifdef INET
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#include <netinet/in.h>
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#include <netinet/if_ether.h>
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#endif
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#include <dev/ath/if_athvar.h>
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#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
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#include <dev/ath/ath_hal/ah_diagcodes.h>
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#include <dev/ath/if_ath_debug.h>
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#include <dev/ath/if_ath_misc.h>
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#include <dev/ath/if_ath_tsf.h>
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#include <dev/ath/if_ath_tx.h>
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#include <dev/ath/if_ath_sysctl.h>
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#include <dev/ath/if_ath_led.h>
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#include <dev/ath/if_ath_keycache.h>
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#include <dev/ath/if_ath_rx.h>
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#include <dev/ath/if_ath_beacon.h>
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#include <dev/ath/if_athdfs.h>
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#ifdef ATH_TX99_DIAG
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#include <dev/ath/ath_tx99/ath_tx99.h>
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#endif
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#include <dev/ath/if_ath_tx_edma.h>
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#ifdef ATH_DEBUG_ALQ
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#include <dev/ath/if_ath_alq.h>
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#endif
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/*
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* some general macros
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*/
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#define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1)
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#define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1)
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/*
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* XXX doesn't belong here, and should be tunable
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*/
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#define ATH_TXSTATUS_RING_SIZE 512
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MALLOC_DECLARE(M_ATHDEV);
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static void ath_edma_tx_processq(struct ath_softc *sc, int dosched);
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static void
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ath_edma_tx_fifo_fill(struct ath_softc *sc, struct ath_txq *txq)
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{
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struct ath_buf *bf;
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int i = 0;
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ATH_TX_LOCK_ASSERT(sc);
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DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: called\n", __func__);
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TAILQ_FOREACH(bf, &txq->axq_q, bf_list) {
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if (txq->axq_fifo_depth >= HAL_TXFIFO_DEPTH)
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break;
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ath_hal_puttxbuf(sc->sc_ah, txq->axq_qnum, bf->bf_daddr);
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#ifdef ATH_DEBUG
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if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
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ath_printtxbuf(sc, bf, txq->axq_qnum, i, 0);
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#endif/* ATH_DEBUG */
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#ifdef ATH_DEBUG_ALQ
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if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC))
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ath_tx_alq_post(sc, bf);
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#endif /* ATH_DEBUG_ALQ */
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txq->axq_fifo_depth++;
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i++;
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}
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if (i > 0)
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ath_hal_txstart(sc->sc_ah, txq->axq_qnum);
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}
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/*
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* Re-initialise the DMA FIFO with the current contents of
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* said TXQ.
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*
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* This should only be called as part of the chip reset path, as it
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* assumes the FIFO is currently empty.
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*/
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static void
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ath_edma_dma_restart(struct ath_softc *sc, struct ath_txq *txq)
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{
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DPRINTF(sc, ATH_DEBUG_RESET, "%s: called: txq=%p, qnum=%d\n",
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__func__,
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txq,
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txq->axq_qnum);
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ATH_TX_LOCK_ASSERT(sc);
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ath_edma_tx_fifo_fill(sc, txq);
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}
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/*
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* Hand off this frame to a hardware queue.
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*
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* Things are a bit hairy in the EDMA world. The TX FIFO is only
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* 8 entries deep, so we need to keep track of exactly what we've
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* pushed into the FIFO and what's just sitting in the TX queue,
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* waiting to go out.
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*
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* So this is split into two halves - frames get appended to the
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* TXQ; then a scheduler is called to push some frames into the
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* actual TX FIFO.
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*/
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static void
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ath_edma_xmit_handoff_hw(struct ath_softc *sc, struct ath_txq *txq,
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struct ath_buf *bf)
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{
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struct ath_hal *ah = sc->sc_ah;
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ATH_TX_LOCK_ASSERT(sc);
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KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
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("%s: busy status 0x%x", __func__, bf->bf_flags));
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/*
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* XXX TODO: write a hard-coded check to ensure that
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* the queue id in the TX descriptor matches txq->axq_qnum.
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*/
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/* Update aggr stats */
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if (bf->bf_state.bfs_aggr)
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txq->axq_aggr_depth++;
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/* Push and update frame stats */
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ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
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/* Only schedule to the FIFO if there's space */
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if (txq->axq_fifo_depth < HAL_TXFIFO_DEPTH) {
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#ifdef ATH_DEBUG
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if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
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ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 0);
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#endif /* ATH_DEBUG */
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#ifdef ATH_DEBUG_ALQ
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if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC))
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ath_tx_alq_post(sc, bf);
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#endif /* ATH_DEBUG_ALQ */
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ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
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txq->axq_fifo_depth++;
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ath_hal_txstart(ah, txq->axq_qnum);
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}
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}
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/*
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* Hand off this frame to a multicast software queue.
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*
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* The EDMA TX CABQ will get a list of chained frames, chained
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* together using the next pointer. The single head of that
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* particular queue is pushed to the hardware CABQ.
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*/
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static void
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ath_edma_xmit_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq,
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struct ath_buf *bf)
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{
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ATH_TX_LOCK_ASSERT(sc);
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KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
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("%s: busy status 0x%x", __func__, bf->bf_flags));
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/*
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* XXX this is mostly duplicated in ath_tx_handoff_mcast().
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*/
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if (ATH_TXQ_FIRST(txq) != NULL) {
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struct ath_buf *bf_last = ATH_TXQ_LAST(txq, axq_q_s);
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struct ieee80211_frame *wh;
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/* mark previous frame */
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wh = mtod(bf_last->bf_m, struct ieee80211_frame *);
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wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA;
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/* sync descriptor to memory */
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bus_dmamap_sync(sc->sc_dmat, bf_last->bf_dmamap,
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BUS_DMASYNC_PREWRITE);
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}
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#ifdef ATH_DEBUG_ALQ
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if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC))
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ath_tx_alq_post(sc, bf);
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#endif /* ATH_DEBUG_ALQ */
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ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
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ath_hal_gettxdesclinkptr(sc->sc_ah, bf->bf_lastds, &txq->axq_link);
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}
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/*
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* Handoff this frame to the hardware.
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*
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* For the multicast queue, this will treat it as a software queue
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* and append it to the list, after updating the MORE_DATA flag
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* in the previous frame. The cabq processing code will ensure
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* that the queue contents gets transferred over.
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*
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* For the hardware queues, this will queue a frame to the queue
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* like before, then populate the FIFO from that. Since the
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* EDMA hardware has 8 FIFO slots per TXQ, this ensures that
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* frames such as management frames don't get prematurely dropped.
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*
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* This does imply that a similar flush-hwq-to-fifoq method will
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* need to be called from the processq function, before the
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* per-node software scheduler is called.
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*/
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static void
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ath_edma_xmit_handoff(struct ath_softc *sc, struct ath_txq *txq,
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struct ath_buf *bf)
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{
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ATH_TX_LOCK_ASSERT(sc);
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DPRINTF(sc, ATH_DEBUG_XMIT_DESC,
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"%s: called; bf=%p, txq=%p, qnum=%d\n",
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__func__,
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bf,
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txq,
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txq->axq_qnum);
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if (txq->axq_qnum == ATH_TXQ_SWQ)
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ath_edma_xmit_handoff_mcast(sc, txq, bf);
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else
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ath_edma_xmit_handoff_hw(sc, txq, bf);
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#if 0
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/*
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* XXX For now this is a placeholder; free the buffer
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* and inform the stack that the TX failed.
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*/
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ath_tx_default_comp(sc, bf, 1);
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#endif
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}
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static int
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ath_edma_setup_txfifo(struct ath_softc *sc, int qnum)
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{
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struct ath_tx_edma_fifo *te = &sc->sc_txedma[qnum];
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te->m_fifo = malloc(sizeof(struct ath_buf *) * HAL_TXFIFO_DEPTH,
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M_ATHDEV,
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M_NOWAIT | M_ZERO);
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if (te->m_fifo == NULL) {
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device_printf(sc->sc_dev, "%s: malloc failed\n",
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__func__);
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return (-ENOMEM);
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}
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/*
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* Set initial "empty" state.
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*/
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te->m_fifo_head = te->m_fifo_tail = te->m_fifo_depth = 0;
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return (0);
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}
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static int
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ath_edma_free_txfifo(struct ath_softc *sc, int qnum)
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{
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struct ath_tx_edma_fifo *te = &sc->sc_txedma[qnum];
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/* XXX TODO: actually deref the ath_buf entries? */
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free(te->m_fifo, M_ATHDEV);
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return (0);
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}
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static int
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ath_edma_dma_txsetup(struct ath_softc *sc)
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{
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int error;
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int i;
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error = ath_descdma_alloc_desc(sc, &sc->sc_txsdma,
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NULL, "txcomp", sc->sc_tx_statuslen, ATH_TXSTATUS_RING_SIZE);
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if (error != 0)
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return (error);
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ath_hal_setuptxstatusring(sc->sc_ah,
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(void *) sc->sc_txsdma.dd_desc,
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sc->sc_txsdma.dd_desc_paddr,
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ATH_TXSTATUS_RING_SIZE);
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for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
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ath_edma_setup_txfifo(sc, i);
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}
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return (0);
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}
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static int
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ath_edma_dma_txteardown(struct ath_softc *sc)
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{
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int i;
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for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
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ath_edma_free_txfifo(sc, i);
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}
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ath_descdma_cleanup(sc, &sc->sc_txsdma, NULL);
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return (0);
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}
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/*
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* Drain all TXQs, potentially after completing the existing completed
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* frames.
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*/
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static void
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ath_edma_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type)
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{
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struct ifnet *ifp = sc->sc_ifp;
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int i;
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DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
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(void) ath_stoptxdma(sc);
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/*
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* If reset type is noloss, the TX FIFO needs to be serviced
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* and those frames need to be handled.
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*
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* Otherwise, just toss everything in each TX queue.
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*/
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if (reset_type == ATH_RESET_NOLOSS) {
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ath_edma_tx_processq(sc, 0);
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} else {
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for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
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if (ATH_TXQ_SETUP(sc, i))
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ath_tx_draintxq(sc, &sc->sc_txq[i]);
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}
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}
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/* XXX dump out the TX completion FIFO contents */
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/* XXX dump out the frames */
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IF_LOCK(&ifp->if_snd);
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ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
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IF_UNLOCK(&ifp->if_snd);
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sc->sc_wd_timer = 0;
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}
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/*
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* TX completion tasklet.
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*/
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static void
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ath_edma_tx_proc(void *arg, int npending)
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{
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struct ath_softc *sc = (struct ath_softc *) arg;
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DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: called, npending=%d\n",
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__func__, npending);
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ath_edma_tx_processq(sc, 1);
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}
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/*
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* Process the TX status queue.
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*/
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static void
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ath_edma_tx_processq(struct ath_softc *sc, int dosched)
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{
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struct ath_hal *ah = sc->sc_ah;
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HAL_STATUS status;
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struct ath_tx_status ts;
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struct ath_txq *txq;
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struct ath_buf *bf;
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struct ieee80211_node *ni;
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int nacked = 0;
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int idx;
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#ifdef ATH_DEBUG
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/* XXX */
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uint32_t txstatus[32];
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#endif
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for (idx = 0; ; idx++) {
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bzero(&ts, sizeof(ts));
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ATH_TXSTATUS_LOCK(sc);
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#ifdef ATH_DEBUG
|
|
ath_hal_gettxrawtxdesc(ah, txstatus);
|
|
#endif
|
|
status = ath_hal_txprocdesc(ah, NULL, (void *) &ts);
|
|
ATH_TXSTATUS_UNLOCK(sc);
|
|
|
|
#ifdef ATH_DEBUG
|
|
if (sc->sc_debug & ATH_DEBUG_TX_PROC)
|
|
ath_printtxstatbuf(sc, NULL, txstatus, ts.ts_queue_id,
|
|
idx, (status == HAL_OK));
|
|
#endif
|
|
|
|
if (status == HAL_EINPROGRESS)
|
|
break;
|
|
|
|
/*
|
|
* If there is an error with this descriptor, continue
|
|
* processing.
|
|
*
|
|
* XXX TBD: log some statistics?
|
|
*/
|
|
if (status == HAL_EIO) {
|
|
device_printf(sc->sc_dev, "%s: invalid TX status?\n",
|
|
__func__);
|
|
continue;
|
|
}
|
|
|
|
#ifdef ATH_DEBUG_ALQ
|
|
if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS))
|
|
if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS,
|
|
sc->sc_tx_statuslen,
|
|
(char *) txstatus);
|
|
#endif /* ATH_DEBUG_ALQ */
|
|
|
|
/*
|
|
* At this point we have a valid status descriptor.
|
|
* The QID and descriptor ID (which currently isn't set)
|
|
* is part of the status.
|
|
*
|
|
* We then assume that the descriptor in question is the
|
|
* -head- of the given QID. Eventually we should verify
|
|
* this by using the descriptor ID.
|
|
*/
|
|
|
|
/*
|
|
* The beacon queue is not currently a "real" queue.
|
|
* Frames aren't pushed onto it and the lock isn't setup.
|
|
* So skip it for now; the beacon handling code will
|
|
* free and alloc more beacon buffers as appropriate.
|
|
*/
|
|
if (ts.ts_queue_id == sc->sc_bhalq)
|
|
continue;
|
|
|
|
txq = &sc->sc_txq[ts.ts_queue_id];
|
|
|
|
ATH_TX_LOCK(sc);
|
|
bf = TAILQ_FIRST(&txq->axq_q);
|
|
|
|
DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: qcuid=%d, bf=%p\n",
|
|
__func__,
|
|
ts.ts_queue_id, bf);
|
|
|
|
/* XXX TODO: actually output debugging info about this */
|
|
|
|
#if 0
|
|
/* XXX assert the buffer/descriptor matches the status descid */
|
|
if (ts.ts_desc_id != bf->bf_descid) {
|
|
device_printf(sc->sc_dev,
|
|
"%s: mismatched descid (qid=%d, tsdescid=%d, "
|
|
"bfdescid=%d\n",
|
|
__func__,
|
|
ts.ts_queue_id,
|
|
ts.ts_desc_id,
|
|
bf->bf_descid);
|
|
}
|
|
#endif
|
|
|
|
/* This removes the buffer and decrements the queue depth */
|
|
ATH_TXQ_REMOVE(txq, bf, bf_list);
|
|
if (bf->bf_state.bfs_aggr)
|
|
txq->axq_aggr_depth--;
|
|
txq->axq_fifo_depth --;
|
|
/* XXX assert FIFO depth >= 0 */
|
|
ATH_TX_UNLOCK(sc);
|
|
|
|
/*
|
|
* First we need to make sure ts_rate is valid.
|
|
*
|
|
* Pre-EDMA chips pass the whole TX descriptor to
|
|
* the proctxdesc function which will then fill out
|
|
* ts_rate based on the ts_finaltsi (final TX index)
|
|
* in the TX descriptor. However the TX completion
|
|
* FIFO doesn't have this information. So here we
|
|
* do a separate HAL call to populate that information.
|
|
*
|
|
* The same problem exists with ts_longretry.
|
|
* The FreeBSD HAL corrects ts_longretry in the HAL layer;
|
|
* the AR9380 HAL currently doesn't. So until the HAL
|
|
* is imported and this can be added, we correct for it
|
|
* here.
|
|
*/
|
|
/* XXX TODO */
|
|
/* XXX faked for now. Ew. */
|
|
if (ts.ts_finaltsi < 4) {
|
|
ts.ts_rate =
|
|
bf->bf_state.bfs_rc[ts.ts_finaltsi].ratecode;
|
|
switch (ts.ts_finaltsi) {
|
|
case 3: ts.ts_longretry +=
|
|
bf->bf_state.bfs_rc[2].tries;
|
|
case 2: ts.ts_longretry +=
|
|
bf->bf_state.bfs_rc[1].tries;
|
|
case 1: ts.ts_longretry +=
|
|
bf->bf_state.bfs_rc[0].tries;
|
|
}
|
|
} else {
|
|
device_printf(sc->sc_dev, "%s: finaltsi=%d\n",
|
|
__func__,
|
|
ts.ts_finaltsi);
|
|
ts.ts_rate = bf->bf_state.bfs_rc[0].ratecode;
|
|
}
|
|
|
|
/*
|
|
* XXX This is terrible.
|
|
*
|
|
* Right now, some code uses the TX status that is
|
|
* passed in here, but the completion handlers in the
|
|
* software TX path also use bf_status.ds_txstat.
|
|
* Ew. That should all go away.
|
|
*
|
|
* XXX It's also possible the rate control completion
|
|
* routine is called twice.
|
|
*/
|
|
memcpy(&bf->bf_status, &ts, sizeof(ts));
|
|
|
|
ni = bf->bf_node;
|
|
|
|
/* Update RSSI */
|
|
/* XXX duplicate from ath_tx_processq */
|
|
if (ni != NULL && ts.ts_status == 0 &&
|
|
((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) {
|
|
nacked++;
|
|
sc->sc_stats.ast_tx_rssi = ts.ts_rssi;
|
|
ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
|
|
ts.ts_rssi);
|
|
}
|
|
|
|
/* Handle frame completion and rate control update */
|
|
ath_tx_process_buf_completion(sc, txq, &ts, bf);
|
|
|
|
/* bf is invalid at this point */
|
|
|
|
/*
|
|
* Now that there's space in the FIFO, let's push some
|
|
* more frames into it.
|
|
*
|
|
* Unfortunately for now, the txq has FIFO and non-FIFO
|
|
* frames in the same linked list, so there's no way
|
|
* to quickly/easily populate frames without walking
|
|
* the queue and skipping 'axq_fifo_depth' frames.
|
|
*
|
|
* So for now, let's only repopulate the FIFO once it
|
|
* is empty. It's sucky for performance but it's enough
|
|
* to begin validating that things are somewhat
|
|
* working.
|
|
*/
|
|
ATH_TX_LOCK(sc);
|
|
if (dosched && txq->axq_fifo_depth == 0) {
|
|
ath_edma_tx_fifo_fill(sc, txq);
|
|
}
|
|
ATH_TX_UNLOCK(sc);
|
|
}
|
|
|
|
sc->sc_wd_timer = 0;
|
|
|
|
if (idx > 0) {
|
|
IF_LOCK(&sc->sc_ifp->if_snd);
|
|
sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
|
|
IF_UNLOCK(&sc->sc_ifp->if_snd);
|
|
}
|
|
|
|
/* Kick software scheduler */
|
|
/*
|
|
* XXX It's inefficient to do this if the FIFO queue is full,
|
|
* but there's no easy way right now to only populate
|
|
* the txq task for _one_ TXQ. This should be fixed.
|
|
*/
|
|
if (dosched)
|
|
taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask);
|
|
}
|
|
|
|
static void
|
|
ath_edma_attach_comp_func(struct ath_softc *sc)
|
|
{
|
|
|
|
TASK_INIT(&sc->sc_txtask, 0, ath_edma_tx_proc, sc);
|
|
}
|
|
|
|
void
|
|
ath_xmit_setup_edma(struct ath_softc *sc)
|
|
{
|
|
|
|
/* Fetch EDMA field and buffer sizes */
|
|
(void) ath_hal_gettxdesclen(sc->sc_ah, &sc->sc_tx_desclen);
|
|
(void) ath_hal_gettxstatuslen(sc->sc_ah, &sc->sc_tx_statuslen);
|
|
(void) ath_hal_getntxmaps(sc->sc_ah, &sc->sc_tx_nmaps);
|
|
|
|
device_printf(sc->sc_dev, "TX descriptor length: %d\n",
|
|
sc->sc_tx_desclen);
|
|
device_printf(sc->sc_dev, "TX status length: %d\n",
|
|
sc->sc_tx_statuslen);
|
|
device_printf(sc->sc_dev, "TX buffers per descriptor: %d\n",
|
|
sc->sc_tx_nmaps);
|
|
|
|
sc->sc_tx.xmit_setup = ath_edma_dma_txsetup;
|
|
sc->sc_tx.xmit_teardown = ath_edma_dma_txteardown;
|
|
sc->sc_tx.xmit_attach_comp_func = ath_edma_attach_comp_func;
|
|
|
|
sc->sc_tx.xmit_dma_restart = ath_edma_dma_restart;
|
|
sc->sc_tx.xmit_handoff = ath_edma_xmit_handoff;
|
|
sc->sc_tx.xmit_drain = ath_edma_tx_drain;
|
|
}
|