4b7fcd31e1
implementations for each of the chips we support. Most chips up through armv6 can use the armv4 implementation which has a single coprocessor opcode for this operation. The rather more complex armv7 implementation comes from netbsd.
80 lines
2.6 KiB
ArmAsm
80 lines
2.6 KiB
ArmAsm
/* $NetBSD: cpufunc_asm_armv4.S,v 1.1 2001/11/10 23:14:09 thorpej Exp $ */
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/*-
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* Copyright (c) 2001 ARM Limited
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* Copyright (c) 1997,1998 Mark Brinicombe.
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* Copyright (c) 1997 Causality Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Causality Limited.
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* 4. The name of Causality Limited may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* ARM9 assembly functions for CPU / MMU / TLB specific operations
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*
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*/
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#include <machine/asm.h>
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__FBSDID("$FreeBSD$");
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/*
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* TLB functions
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*/
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ENTRY(armv4_tlb_flushID)
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mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
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RET
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END(armv4_tlb_flushID)
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ENTRY(armv4_tlb_flushI)
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mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
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RET
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END(armv4_tlb_flushI)
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ENTRY(armv4_tlb_flushD)
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mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
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RET
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END(armv4_tlb_flushD)
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ENTRY(armv4_tlb_flushD_SE)
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mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
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RET
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END(armv4_tlb_flushD_SE)
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/*
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* Other functions
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*/
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ENTRY(armv4_drain_writebuf)
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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RET
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END(armv4_drain_writebuf)
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ENTRY(armv4_idcache_inv_all)
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* invalidate all I+D cache */
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RET
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END(armv4_drain_writebuf)
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