d1693e1701
There is some unresolved badness that has been eluding me, particularly affecting uniprocessor kernels. Turning off PG_G helped (which is a bad sign) but didn't solve it entirely. Userland programs still crashed.
457 lines
10 KiB
ArmAsm
457 lines
10 KiB
ArmAsm
/*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $FreeBSD$
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*/
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#include <machine/apic.h>
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#include <machine/smp.h>
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/* convert an absolute IRQ# into a bitmask */
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#define IRQ_BIT(irq_num) (1 << (irq_num))
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/* make an index into the IO APIC from the IRQ# */
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#define REDTBL_IDX(irq_num) (0x10 + ((irq_num) * 2))
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/*
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*
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*/
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#define PUSH_FRAME \
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pushl $0 ; /* dummy error code */ \
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pushl $0 ; /* dummy trap type */ \
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pushal ; \
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pushl %ds ; /* save data and extra segments ... */ \
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pushl %es ; \
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pushl %fs
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#define POP_FRAME \
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popl %fs ; \
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popl %es ; \
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popl %ds ; \
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popal ; \
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addl $4+4,%esp
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/*
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* Macros for interrupt entry, call to handler, and exit.
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*/
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#define FAST_INTR(irq_num, vec_name) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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PUSH_FRAME ; \
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movl $KDSEL,%eax ; \
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mov %ax,%ds ; \
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mov %ax,%es ; \
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movl $KPSEL,%eax ; \
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mov %ax,%fs ; \
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FAKE_MCOUNT(13*4(%esp)) ; \
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call critical_enter ; \
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movl PCPU(CURTHREAD),%ebx ; \
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incl TD_INTR_NESTING_LEVEL(%ebx) ; \
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pushl intr_unit + (irq_num) * 4 ; \
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call *intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
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addl $4, %esp ; \
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movl $0, lapic+LA_EOI ; \
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lock ; \
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incl cnt+V_INTR ; /* book-keeping can wait */ \
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movl intr_countp + (irq_num) * 4, %eax ; \
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lock ; \
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incl (%eax) ; \
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decl TD_INTR_NESTING_LEVEL(%ebx) ; \
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call critical_exit ; \
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MEXITCOUNT ; \
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jmp doreti
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#define IOAPICADDR(irq_num) CNAME(int_to_apicintpin) + 16 * (irq_num) + 8
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#define REDIRIDX(irq_num) CNAME(int_to_apicintpin) + 16 * (irq_num) + 12
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#define MASK_IRQ(irq_num) \
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ICU_LOCK ; /* into critical reg */ \
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testl $IRQ_BIT(irq_num), apic_imen ; \
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jne 7f ; /* masked, don't mask */ \
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orl $IRQ_BIT(irq_num), apic_imen ; /* set the mask bit */ \
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movl IOAPICADDR(irq_num), %ecx ; /* ioapic addr */ \
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movl REDIRIDX(irq_num), %eax ; /* get the index */ \
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movl %eax, (%ecx) ; /* write the index */ \
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movl IOAPIC_WINDOW(%ecx), %eax ; /* current value */ \
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orl $IOART_INTMASK, %eax ; /* set the mask */ \
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movl %eax, IOAPIC_WINDOW(%ecx) ; /* new value */ \
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7: ; /* already masked */ \
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ICU_UNLOCK
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/*
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* Test to see whether we are handling an edge or level triggered INT.
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* Level-triggered INTs must still be masked as we don't clear the source,
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* and the EOI cycle would cause redundant INTs to occur.
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*/
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#define MASK_LEVEL_IRQ(irq_num) \
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testl $IRQ_BIT(irq_num), apic_pin_trigger ; \
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jz 9f ; /* edge, don't mask */ \
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MASK_IRQ(irq_num) ; \
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9:
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#ifdef APIC_INTR_REORDER
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#define EOI_IRQ(irq_num) \
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movl apic_isrbit_location + 8 * (irq_num), %eax ; \
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movl (%eax), %eax ; \
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testl apic_isrbit_location + 4 + 8 * (irq_num), %eax ; \
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jz 9f ; /* not active */ \
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movl $0, lapic+LA_EOI ; \
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9:
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#else
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#define EOI_IRQ(irq_num) \
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testl $IRQ_BIT(irq_num), lapic+LA_ISR1; \
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jz 9f ; /* not active */ \
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movl $0, lapic+LA_EOI; \
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9:
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#endif
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/*
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* Test to see if the source is currently masked, clear if so.
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*/
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#define UNMASK_IRQ(irq_num) \
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ICU_LOCK ; /* into critical reg */ \
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testl $IRQ_BIT(irq_num), _apic_imen ; \
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je 7f ; /* bit clear, not masked */ \
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andl $~IRQ_BIT(irq_num), _apic_imen ;/* clear mask bit */ \
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movl IOAPICADDR(irq_num), %ecx ; /* ioapic addr */ \
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movl REDIRIDX(irq_num), %eax ; /* get the index */ \
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movl %eax, (%ecx) ; /* write the index */ \
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movl IOAPIC_WINDOW(%ecx), %eax ; /* current value */ \
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andl $~IOART_INTMASK, %eax ; /* clear the mask */ \
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movl %eax, IOAPIC_WINDOW(%ecx) ; /* new value */ \
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7: ; /* already unmasked */ \
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ICU_UNLOCK
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/*
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* Slow, threaded interrupts.
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*
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* XXX Most of the parameters here are obsolete. Fix this when we're
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* done.
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* XXX we really shouldn't return via doreti if we just schedule the
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* interrupt handler and don't run anything. We could just do an
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* iret. FIXME.
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*/
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#define INTR(irq_num, vec_name, maybe_extra_ipending) \
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.text ; \
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SUPERALIGN_TEXT ; \
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/* _XintrNN: entry point used by IDT/HWIs via _vec[]. */ \
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IDTVEC(vec_name) ; \
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PUSH_FRAME ; \
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movl $KDSEL, %eax ; /* reload with kernel's data segment */ \
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mov %ax, %ds ; \
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mov %ax, %es ; \
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movl $KPSEL, %eax ; \
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mov %ax, %fs ; \
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; \
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maybe_extra_ipending ; \
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; \
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MASK_LEVEL_IRQ(irq_num) ; \
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EOI_IRQ(irq_num) ; \
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0: ; \
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movl PCPU(CURTHREAD),%ebx ; \
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incl TD_INTR_NESTING_LEVEL(%ebx) ; \
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; \
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FAKE_MCOUNT(13*4(%esp)) ; /* XXX avoid dbl cnt */ \
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pushl $irq_num; /* pass the IRQ */ \
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call sched_ithd ; \
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addl $4, %esp ; /* discard the parameter */ \
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; \
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decl TD_INTR_NESTING_LEVEL(%ebx) ; \
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MEXITCOUNT ; \
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jmp doreti
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/*
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* Handle "spurious INTerrupts".
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* Notes:
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* This is different than the "spurious INTerrupt" generated by an
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* 8259 PIC for missing INTs. See the APIC documentation for details.
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* This routine should NOT do an 'EOI' cycle.
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*/
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.text
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SUPERALIGN_TEXT
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.globl Xspuriousint
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Xspuriousint:
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/* No EOI cycle used here */
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iret
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/*
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* Handle TLB shootdowns.
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*/
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.text
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SUPERALIGN_TEXT
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.globl Xinvltlb
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Xinvltlb:
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pushl %eax
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#ifdef COUNT_XINVLTLB_HITS
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pushl %fs
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movl $KPSEL, %eax
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mov %ax, %fs
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movl PCPU(CPUID), %eax
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popl %fs
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ss
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incl _xhits(,%eax,4)
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#endif /* COUNT_XINVLTLB_HITS */
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movl %cr3, %eax /* invalidate the TLB */
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movl %eax, %cr3
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ss /* stack segment, avoid %ds load */
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movl $0, lapic+LA_EOI /* End Of Interrupt to APIC */
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popl %eax
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iret
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/*
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* Forward hardclock to another CPU. Pushes a trapframe and calls
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* forwarded_hardclock().
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*/
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.text
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SUPERALIGN_TEXT
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.globl Xhardclock
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Xhardclock:
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PUSH_FRAME
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movl $KDSEL, %eax /* reload with kernel's data segment */
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mov %ax, %ds
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mov %ax, %es
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movl $KPSEL, %eax
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mov %ax, %fs
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movl $0, lapic+LA_EOI /* End Of Interrupt to APIC */
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movl PCPU(CURTHREAD),%ebx
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incl TD_INTR_NESTING_LEVEL(%ebx)
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call forwarded_hardclock
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decl TD_INTR_NESTING_LEVEL(%ebx)
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MEXITCOUNT
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jmp doreti
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/*
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* Forward statclock to another CPU. Pushes a trapframe and calls
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* forwarded_statclock().
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*/
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.text
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SUPERALIGN_TEXT
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.globl Xstatclock
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Xstatclock:
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PUSH_FRAME
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movl $KDSEL, %eax /* reload with kernel's data segment */
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mov %ax, %ds
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mov %ax, %es
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movl $KPSEL, %eax
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mov %ax, %fs
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movl $0, lapic+LA_EOI /* End Of Interrupt to APIC */
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FAKE_MCOUNT(13*4(%esp))
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movl PCPU(CURTHREAD),%ebx
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incl TD_INTR_NESTING_LEVEL(%ebx)
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call forwarded_statclock
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decl TD_INTR_NESTING_LEVEL(%ebx)
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MEXITCOUNT
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jmp doreti
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/*
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* Executed by a CPU when it receives an Xcpuast IPI from another CPU,
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*
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* The other CPU has already executed aston() or need_resched() on our
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* current process, so we simply need to ack the interrupt and return
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* via doreti to run ast().
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*/
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.text
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SUPERALIGN_TEXT
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.globl Xcpuast
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Xcpuast:
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PUSH_FRAME
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movl $KDSEL, %eax
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mov %ax, %ds /* use KERNEL data segment */
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mov %ax, %es
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movl $KPSEL, %eax
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mov %ax, %fs
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movl $0, lapic+LA_EOI /* End Of Interrupt to APIC */
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FAKE_MCOUNT(13*4(%esp))
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MEXITCOUNT
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jmp doreti
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/*
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* Executed by a CPU when it receives an Xcpustop IPI from another CPU,
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*
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* - Signals its receipt.
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* - Waits for permission to restart.
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* - Signals its restart.
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*/
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.text
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SUPERALIGN_TEXT
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.globl Xcpustop
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Xcpustop:
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pushl %ebp
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movl %esp, %ebp
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pushl %eax
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pushl %ecx
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pushl %edx
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pushl %ds /* save current data segment */
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pushl %fs
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movl $KDSEL, %eax
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mov %ax, %ds /* use KERNEL data segment */
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movl $KPSEL, %eax
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mov %ax, %fs
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movl $0, lapic+LA_EOI /* End Of Interrupt to APIC */
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movl PCPU(CPUID), %eax
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imull $PCB_SIZE, %eax
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leal CNAME(stoppcbs)(%eax), %eax
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pushl %eax
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call CNAME(savectx) /* Save process context */
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addl $4, %esp
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movl PCPU(CPUID), %eax
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lock
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btsl %eax, CNAME(stopped_cpus) /* stopped_cpus |= (1<<id) */
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1:
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btl %eax, CNAME(started_cpus) /* while (!(started_cpus & (1<<id))) */
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jnc 1b
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lock
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btrl %eax, CNAME(started_cpus) /* started_cpus &= ~(1<<id) */
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lock
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btrl %eax, CNAME(stopped_cpus) /* stopped_cpus &= ~(1<<id) */
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test %eax, %eax
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jnz 2f
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movl CNAME(cpustop_restartfunc), %eax
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test %eax, %eax
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jz 2f
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movl $0, CNAME(cpustop_restartfunc) /* One-shot */
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call *%eax
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2:
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popl %fs
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popl %ds /* restore previous data segment */
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popl %edx
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popl %ecx
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popl %eax
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movl %ebp, %esp
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popl %ebp
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iret
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MCOUNT_LABEL(bintr)
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FAST_INTR(0,fastintr0)
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FAST_INTR(1,fastintr1)
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FAST_INTR(2,fastintr2)
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FAST_INTR(3,fastintr3)
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FAST_INTR(4,fastintr4)
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FAST_INTR(5,fastintr5)
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FAST_INTR(6,fastintr6)
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FAST_INTR(7,fastintr7)
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FAST_INTR(8,fastintr8)
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FAST_INTR(9,fastintr9)
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FAST_INTR(10,fastintr10)
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FAST_INTR(11,fastintr11)
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FAST_INTR(12,fastintr12)
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FAST_INTR(13,fastintr13)
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FAST_INTR(14,fastintr14)
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FAST_INTR(15,fastintr15)
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FAST_INTR(16,fastintr16)
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FAST_INTR(17,fastintr17)
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FAST_INTR(18,fastintr18)
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FAST_INTR(19,fastintr19)
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FAST_INTR(20,fastintr20)
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FAST_INTR(21,fastintr21)
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FAST_INTR(22,fastintr22)
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FAST_INTR(23,fastintr23)
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FAST_INTR(24,fastintr24)
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FAST_INTR(25,fastintr25)
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FAST_INTR(26,fastintr26)
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FAST_INTR(27,fastintr27)
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FAST_INTR(28,fastintr28)
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FAST_INTR(29,fastintr29)
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FAST_INTR(30,fastintr30)
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FAST_INTR(31,fastintr31)
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#define CLKINTR_PENDING movl $1,CNAME(clkintr_pending)
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/* Threaded interrupts */
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INTR(0,intr0, CLKINTR_PENDING)
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INTR(1,intr1,)
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INTR(2,intr2,)
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INTR(3,intr3,)
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INTR(4,intr4,)
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INTR(5,intr5,)
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INTR(6,intr6,)
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INTR(7,intr7,)
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INTR(8,intr8,)
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INTR(9,intr9,)
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INTR(10,intr10,)
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INTR(11,intr11,)
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INTR(12,intr12,)
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INTR(13,intr13,)
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INTR(14,intr14,)
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INTR(15,intr15,)
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INTR(16,intr16,)
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INTR(17,intr17,)
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INTR(18,intr18,)
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INTR(19,intr19,)
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INTR(20,intr20,)
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INTR(21,intr21,)
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INTR(22,intr22,)
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INTR(23,intr23,)
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INTR(24,intr24,)
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INTR(25,intr25,)
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INTR(26,intr26,)
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INTR(27,intr27,)
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INTR(28,intr28,)
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INTR(29,intr29,)
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INTR(30,intr30,)
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INTR(31,intr31,)
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MCOUNT_LABEL(eintr)
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/*
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* Executed by a CPU when it receives a RENDEZVOUS IPI from another CPU.
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*
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* - Calls the generic rendezvous action function.
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*/
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.text
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SUPERALIGN_TEXT
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.globl Xrendezvous
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Xrendezvous:
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PUSH_FRAME
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movl $KDSEL, %eax
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mov %ax, %ds /* use KERNEL data segment */
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mov %ax, %es
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movl $KPSEL, %eax
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mov %ax, %fs
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call smp_rendezvous_action
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movl $0, lapic+LA_EOI /* End Of Interrupt to APIC */
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POP_FRAME
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iret
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.data
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#ifdef COUNT_XINVLTLB_HITS
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.globl _xhits
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_xhits:
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.space (NCPU * 4), 0
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#endif /* COUNT_XINVLTLB_HITS */
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.globl apic_pin_trigger
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apic_pin_trigger:
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.long 0
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.text
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