507 lines
20 KiB
C
507 lines
20 KiB
C
/*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_ATH_AR5416REG_H
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#define _DEV_ATH_AR5416REG_H
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#include <dev/ath/ath_hal/ar5212/ar5212reg.h>
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/*
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* Register added starting with the AR5416
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*/
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#define AR_MIRT 0x0020 /* interrupt rate threshold */
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#define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */
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#define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */
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#define AR_GTXTO 0x0064 /* global transmit timeout */
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#define AR_GTTM 0x0068 /* global transmit timeout mode */
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#define AR_CST 0x006C /* carrier sense timeout */
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#define AR_MAC_LED 0x1f04 /* LED control */
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#define AR5416_PCIE_PM_CTRL 0x4014
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#define AR_AHB_MODE 0x4024 /* AHB mode for dma */
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#define AR_INTR_SYNC_CAUSE_CLR 0x4028 /* clear interrupt */
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#define AR_INTR_SYNC_CAUSE 0x4028 /* check pending interrupts */
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#define AR_INTR_SYNC_ENABLE 0x402c /* enable interrupts */
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#define AR_INTR_ASYNC_MASK 0x4030 /* asynchronous interrupt mask */
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#define AR_INTR_SYNC_MASK 0x4034 /* synchronous interrupt mask */
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#define AR_INTR_ASYNC_CAUSE 0x4038 /* check pending interrupts */
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#define AR_INTR_ASYNC_ENABLE 0x403c /* enable interrupts */
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#define AR5416_PCIE_SERDES 0x4040
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#define AR5416_PCIE_SERDES2 0x4044
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#define AR_GPIO_IN 0x4048 /* GPIO input register */
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#define AR_GPIO_INTR_OUT 0x404c /* GPIO output register */
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#define AR_EEPROM_STATUS_DATA 0x407c
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#define AR_OBS 0x4080
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#define AR_RTC_RC 0x7000 /* reset control */
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#define AR_RTC_PLL_CONTROL 0x7014
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#define AR_RTC_RESET 0x7040 /* RTC reset register */
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#define AR_RTC_STATUS 0x7044 /* system sleep status */
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#define AR_RTC_SLEEP_CLK 0x7048
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#define AR_RTC_FORCE_WAKE 0x704c /* control MAC force wake */
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#define AR_RTC_INTR_CAUSE 0x7050 /* RTC interrupt cause/clear */
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#define AR_RTC_INTR_ENABLE 0x7054 /* RTC interrupt enable */
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#define AR_RTC_INTR_MASK 0x7058 /* RTC interrupt mask */
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/* AR9280: rf long shift registers */
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#define AR_AN_RF2G1_CH0 0x7810
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#define AR_AN_RF5G1_CH0 0x7818
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#define AR_AN_RF2G1_CH1 0x7834
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#define AR_AN_RF5G1_CH1 0x783C
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#define AR_AN_TOP2 0x7894
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#define AR_AN_SYNTH9 0x7868
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#define AR9285_AN_RF2G3 0x7828
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#define AR9285_AN_TOP3 0x786c
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#define AR_RESET_TSF 0x8020
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#define AR_RXFIFO_CFG 0x8114
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#define AR_PHY_ERR_1 0x812c
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#define AR_PHY_ERR_MASK_1 0x8130 /* mask for AR_PHY_ERR_1 */
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#define AR_PHY_ERR_2 0x8134
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#define AR_PHY_ERR_MASK_2 0x8138 /* mask for AR_PHY_ERR_2 */
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#define AR_TSFOOR_THRESHOLD 0x813c
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#define AR_PHY_ERR_3 0x8168
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#define AR_PHY_ERR_MASK_3 0x816c /* mask for AR_PHY_ERR_3 */
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#define AR_TXOP_X 0x81ec /* txop for legacy non-qos */
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#define AR_TXOP_0_3 0x81f0 /* txop for various tid's */
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#define AR_TXOP_4_7 0x81f4
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#define AR_TXOP_8_11 0x81f8
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#define AR_TXOP_12_15 0x81fc
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/* generic timers based on tsf - all uS */
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#define AR_NEXT_TBTT 0x8200
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#define AR_NEXT_DBA 0x8204
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#define AR_NEXT_SWBA 0x8208
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#define AR_NEXT_CFP 0x8208
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#define AR_NEXT_HCF 0x820C
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#define AR_NEXT_TIM 0x8210
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#define AR_NEXT_DTIM 0x8214
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#define AR_NEXT_QUIET 0x8218
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#define AR_NEXT_NDP 0x821C
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#define AR5416_BEACON_PERIOD 0x8220
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#define AR_DBA_PERIOD 0x8224
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#define AR_SWBA_PERIOD 0x8228
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#define AR_HCF_PERIOD 0x822C
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#define AR_TIM_PERIOD 0x8230
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#define AR_DTIM_PERIOD 0x8234
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#define AR_QUIET_PERIOD 0x8238
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#define AR_NDP_PERIOD 0x823C
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#define AR_TIMER_MODE 0x8240
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#define AR_SLP32_MODE 0x8244
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#define AR_SLP32_WAKE 0x8248
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#define AR_SLP32_INC 0x824c
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#define AR_SLP_CNT 0x8250 /* 32kHz cycles with mac asleep */
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#define AR_SLP_CYCLE_CNT 0x8254 /* absolute number of 32kHz cycles */
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#define AR_SLP_MIB_CTRL 0x8258
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#define AR_2040_MODE 0x8318
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#define AR_EXTRCCNT 0x8328 /* extension channel rx clear count */
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#define AR_SELFGEN_MASK 0x832c /* rx and cal chain masks */
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#define AR_PCU_TXBUF_CTRL 0x8340
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/* DMA & PCI Registers in PCI space (usable during sleep)*/
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#define AR_RC_AHB 0x00000001 /* AHB reset */
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#define AR_RC_APB 0x00000002 /* APB reset */
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#define AR_RC_HOSTIF 0x00000100 /* host interface reset */
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#define AR_MIRT_VAL 0x0000ffff /* in uS */
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#define AR_MIRT_VAL_S 16
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#define AR_TIMT_LAST 0x0000ffff /* Last packet threshold */
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#define AR_TIMT_LAST_S 0
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#define AR_TIMT_FIRST 0xffff0000 /* First packet threshold */
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#define AR_TIMT_FIRST_S 16
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#define AR_RIMT_LAST 0x0000ffff /* Last packet threshold */
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#define AR_RIMT_LAST_S 0
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#define AR_RIMT_FIRST 0xffff0000 /* First packet threshold */
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#define AR_RIMT_FIRST_S 16
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#define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs)
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#define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs)
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#define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit
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#define AR_GTTM_USEC 0x00000001 // usec strobe
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#define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle
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#define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low
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#define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe
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#define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs)
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#define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs)
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#define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit
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/* MAC tx DMA size config */
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#define AR_TXCFG_DMASZ_MASK 0x00000003
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#define AR_TXCFG_DMASZ_4B 0
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#define AR_TXCFG_DMASZ_8B 1
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#define AR_TXCFG_DMASZ_16B 2
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#define AR_TXCFG_DMASZ_32B 3
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#define AR_TXCFG_DMASZ_64B 4
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#define AR_TXCFG_DMASZ_128B 5
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#define AR_TXCFG_DMASZ_256B 6
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#define AR_TXCFG_DMASZ_512B 7
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#define AR_TXCFG_ATIM_TXPOLICY 0x00000800
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/* MAC rx DMA size config */
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#define AR_RXCFG_DMASZ_MASK 0x00000007
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#define AR_RXCFG_DMASZ_4B 0
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#define AR_RXCFG_DMASZ_8B 1
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#define AR_RXCFG_DMASZ_16B 2
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#define AR_RXCFG_DMASZ_32B 3
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#define AR_RXCFG_DMASZ_64B 4
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#define AR_RXCFG_DMASZ_128B 5
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#define AR_RXCFG_DMASZ_256B 6
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#define AR_RXCFG_DMASZ_512B 7
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/* MAC Led registers */
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#define AR_MAC_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */
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#define AR_MAC_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */
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#define AR_MAC_LED_MODE 0x00000380 /* LED mode select */
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#define AR_MAC_LED_MODE_S 7
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#define AR_MAC_LED_MODE_PROP 0 /* Blink prop to filtered tx/rx */
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#define AR_MAC_LED_MODE_RPROP 1 /* Blink prop to unfiltered tx/rx */
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#define AR_MAC_LED_MODE_SPLIT 2 /* Blink power for tx/net for rx */
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#define AR_MAC_LED_MODE_RAND 3 /* Blink randomly */
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#define AR_MAC_LED_MODE_POWON 5 /* Power LED on (s/w control) */
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#define AR_MAC_LED_MODE_NETON 6 /* Network LED on (s/w control) */
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#define AR_MAC_LED_ASSOC 0x00000c00
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#define AR_MAC_LED_ASSOC_NONE 0x00000000 /* STA is not associated or trying */
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#define AR_MAC_LED_ASSOC_ACTIVE 0x00000400 /* STA is associated */
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#define AR_MAC_LED_ASSOC_PEND 0x00000800 /* STA is trying to associate */
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#define AR_MAC_LED_ASSOC_S 10
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#define AR_AHB_EXACT_WR_EN 0x00000000 /* write exact bytes */
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#define AR_AHB_BUF_WR_EN 0x00000001 /* buffer write upto cacheline*/
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#define AR_AHB_EXACT_RD_EN 0x00000000 /* read exact bytes */
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#define AR_AHB_CACHELINE_RD_EN 0x00000002 /* read upto end of cacheline */
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#define AR_AHB_PREFETCH_RD_EN 0x00000004 /* prefetch upto page boundary*/
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#define AR_AHB_PAGE_SIZE_1K 0x00000000 /* set page-size as 1k */
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#define AR_AHB_PAGE_SIZE_2K 0x00000008 /* set page-size as 2k */
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#define AR_AHB_PAGE_SIZE_4K 0x00000010 /* set page-size as 4k */
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/* MAC PCU Registers */
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#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 /* Don't replace seq num */
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/* Extended PCU DIAG_SW control fields */
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#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 /* dual chain channel info */
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#define AR_DIAG_RX_ABORT 0x02000000 /* abort rx */
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#define AR_DIAG_SATURATE_CCNT 0x04000000 /* sat. cycle cnts (no shift) */
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#define AR_DIAG_OBS_PT_SEL2 0x08000000 /* observation point sel */
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#define AR_DIAG_RXCLEAR_CTL_LOW 0x10000000 /* force rx_clear(ctl) low/busy */
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#define AR_DIAG_RXCLEAR_EXT_LOW 0x20000000 /* force rx_clear(ext) low/busy */
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#define AR_TXOP_X_VAL 0x000000FF
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#define AR_RESET_TSF_ONCE 0x01000000 /* reset tsf once; self-clears*/
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/* Interrupts */
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#define AR_ISR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */
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#define AR_ISR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */
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#define AR_ISR_TXINTM 0x40000000 /* Tx int after mitigation */
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#define AR_ISR_RXINTM 0x80000000 /* Rx int after mitigation */
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#define AR_ISR_S2_CST 0x00400000 /* Carrier sense timeout */
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#define AR_ISR_S2_GTT 0x00800000 /* Global transmit timeout */
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#define AR_ISR_S2_TSFOOR 0x40000000 /* RX TSF out of range */
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#define AR_INTR_SPURIOUS 0xffffffff
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#define AR_INTR_RTC_IRQ 0x00000001 /* rtc in shutdown state */
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#define AR_INTR_MAC_IRQ 0x00000002 /* pending mac interrupt */
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#define AR_INTR_EEP_PROT_ACCESS 0x00000004 /* eeprom protected access */
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#define AR_INTR_MAC_AWAKE 0x00020000 /* mac is awake */
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#define AR_INTR_MAC_ASLEEP 0x00040000 /* mac is asleep */
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/* Interrupt Mask Registers */
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#define AR_IMR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */
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#define AR_IMR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */
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#define AR_IMR_TXINTM 0x40000000 /* Tx int after mitigation */
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#define AR_IMR_RXINTM 0x80000000 /* Rx int after mitigation */
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#define AR_IMR_S2_CST 0x00400000 /* Carrier sense timeout */
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#define AR_IMR_S2_GTT 0x00800000 /* Global transmit timeout */
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/* synchronous interrupt signals */
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#define AR_INTR_SYNC_RTC_IRQ 0x00000001
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#define AR_INTR_SYNC_MAC_IRQ 0x00000002
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#define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004
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#define AR_INTR_SYNC_APB_TIMEOUT 0x00000008
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#define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010
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#define AR_INTR_SYNC_HOST1_FATAL 0x00000020
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#define AR_INTR_SYNC_HOST1_PERR 0x00000040
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#define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080
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#define AR_INTR_SYNC_RADM_CPL_EP 0x00000100
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#define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200
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#define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400
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#define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800
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#define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000
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#define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000
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#define AR_INTR_SYNC_PM_ACCESS 0x00004000
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#define AR_INTR_SYNC_MAC_AWAKE 0x00008000
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#define AR_INTR_SYNC_MAC_ASLEEP 0x00010000
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#define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000
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#define AR_INTR_SYNC_ALL 0x0003FFFF
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/* default synchronous interrupt signals enabled */
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#define AR_INTR_SYNC_DEFAULT \
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(AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR | \
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AR_INTR_SYNC_RADM_CPL_EP | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \
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AR_INTR_SYNC_RADM_CPL_TLP_ABORT | AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \
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AR_INTR_SYNC_RADM_CPL_TIMEOUT | AR_INTR_SYNC_LOCAL_TIMEOUT | \
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AR_INTR_SYNC_MAC_SLEEP_ACCESS)
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/* RTC registers */
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#define AR_RTC_RC_M 0x00000003
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#define AR_RTC_RC_MAC_WARM 0x00000001
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#define AR_RTC_RC_MAC_COLD 0x00000002
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#define AR_RTC_PLL_DIV 0x0000001f
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#define AR_RTC_PLL_DIV_S 0
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#define AR_RTC_PLL_DIV2 0x00000020
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#define AR_RTC_PLL_REFDIV_5 0x000000c0
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#define AR_RTC_SOWL_PLL_DIV 0x000003ff
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#define AR_RTC_SOWL_PLL_DIV_S 0
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#define AR_RTC_SOWL_PLL_REFDIV 0x00003C00
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#define AR_RTC_SOWL_PLL_REFDIV_S 10
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#define AR_RTC_SOWL_PLL_CLKSEL 0x0000C000
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#define AR_RTC_SOWL_PLL_CLKSEL_S 14
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#define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */
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#define AR_RTC_PM_STATUS_M 0x0000000f /* Pwr Mgmt Status */
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#define AR_RTC_STATUS_M 0x0000003f /* RTC Status */
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#define AR_RTC_STATUS_SHUTDOWN 0x00000001
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#define AR_RTC_STATUS_ON 0x00000002
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#define AR_RTC_STATUS_SLEEP 0x00000004
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#define AR_RTC_STATUS_WAKEUP 0x00000008
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#define AR_RTC_STATUS_COLDRESET 0x00000010 /* Not currently used */
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#define AR_RTC_STATUS_PLLCHANGE 0x00000020 /* Not currently used */
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#define AR_RTC_SLEEP_DERIVED_CLK 0x2
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#define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */
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#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */
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#define AR_RTC_PLL_CLKSEL 0x00000300
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#define AR_RTC_PLL_CLKSEL_S 8
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/* AR9280: rf long shift registers */
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#define AR_AN_RF2G1_CH0_OB 0x03800000
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#define AR_AN_RF2G1_CH0_OB_S 23
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#define AR_AN_RF2G1_CH0_DB 0x1C000000
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#define AR_AN_RF2G1_CH0_DB_S 26
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#define AR_AN_RF5G1_CH0_OB5 0x00070000
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#define AR_AN_RF5G1_CH0_OB5_S 16
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#define AR_AN_RF5G1_CH0_DB5 0x00380000
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#define AR_AN_RF5G1_CH0_DB5_S 19
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#define AR_AN_RF2G1_CH1_OB 0x03800000
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#define AR_AN_RF2G1_CH1_OB_S 23
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#define AR_AN_RF2G1_CH1_DB 0x1C000000
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#define AR_AN_RF2G1_CH1_DB_S 26
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#define AR_AN_RF5G1_CH1_OB5 0x00070000
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#define AR_AN_RF5G1_CH1_OB5_S 16
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#define AR_AN_RF5G1_CH1_DB5 0x00380000
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#define AR_AN_RF5G1_CH1_DB5_S 19
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#define AR_AN_TOP2_XPABIAS_LVL 0xC0000000
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#define AR_AN_TOP2_XPABIAS_LVL_S 30
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#define AR_AN_TOP2_LOCALBIAS 0x00200000
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#define AR_AN_TOP2_LOCALBIAS_S 21
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#define AR_AN_TOP2_PWDCLKIND 0x00400000
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#define AR_AN_TOP2_PWDCLKIND_S 22
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#define AR_AN_SYNTH9_REFDIVA 0xf8000000
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#define AR_AN_SYNTH9_REFDIVA_S 27
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/* AR9285 Analog registers */
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#define AR9285_AN_RF2G3_OB_0 0x00E00000
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#define AR9285_AN_RF2G3_OB_0_S 21
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#define AR9285_AN_RF2G3_OB_1 0x001C0000
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#define AR9285_AN_RF2G3_OB_1_S 18
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#define AR9285_AN_RF2G3_OB_2 0x00038000
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#define AR9285_AN_RF2G3_OB_2_S 15
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#define AR9285_AN_RF2G3_OB_3 0x00007000
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#define AR9285_AN_RF2G3_OB_3_S 12
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#define AR9285_AN_RF2G3_OB_4 0x00000E00
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#define AR9285_AN_RF2G3_OB_4_S 9
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#define AR9285_AN_RF2G3_DB1_0 0x000001C0
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#define AR9285_AN_RF2G3_DB1_0_S 6
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#define AR9285_AN_RF2G3_DB1_1 0x00000038
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#define AR9285_AN_RF2G3_DB1_1_S 3
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#define AR9285_AN_RF2G3_DB1_2 0x00000007
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#define AR9285_AN_RF2G3_DB1_2_S 0
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#define AR9285_AN_RF2G4 0x782C
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#define AR9285_AN_RF2G4_DB1_3 0xE0000000
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#define AR9285_AN_RF2G4_DB1_3_S 29
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#define AR9285_AN_RF2G4_DB1_4 0x1C000000
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#define AR9285_AN_RF2G4_DB1_4_S 26
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#define AR9285_AN_RF2G4_DB2_0 0x03800000
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#define AR9285_AN_RF2G4_DB2_0_S 23
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#define AR9285_AN_RF2G4_DB2_1 0x00700000
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#define AR9285_AN_RF2G4_DB2_1_S 20
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#define AR9285_AN_RF2G4_DB2_2 0x000E0000
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#define AR9285_AN_RF2G4_DB2_2_S 17
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#define AR9285_AN_RF2G4_DB2_3 0x0001C000
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#define AR9285_AN_RF2G4_DB2_3_S 14
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#define AR9285_AN_RF2G4_DB2_4 0x00003800
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#define AR9285_AN_RF2G4_DB2_4_S 11
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#define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C
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#define AR9285_AN_TOP3_XPABIAS_LVL_S 2
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/* Sleep control */
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#define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */
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#define AR5416_SLEEP1_CAB_TIMEOUT_S 22
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#define AR5416_SLEEP2_BEACON_TIMEOUT 0xFFE00000 /* Beacon timeout (TU)*/
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#define AR5416_SLEEP2_BEACON_TIMEOUT_S 22
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/* Sleep Registers */
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#define AR_SLP32_HALFCLK_LATENCY 0x000FFFFF /* rising <-> falling edge */
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#define AR_SLP32_ENA 0x00100000
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#define AR_SLP32_TSF_WRITE_STATUS 0x00200000 /* tsf update in progress */
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#define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF /* time to wake crystal */
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#define AR_SLP32_TST_INC 0x000FFFFF
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#define AR_SLP_MIB_CLEAR 0x00000001 /* clear pending */
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#define AR_SLP_MIB_PENDING 0x00000002 /* clear counters */
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#define AR_TIMER_MODE_TBTT 0x00000001
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#define AR_TIMER_MODE_DBA 0x00000002
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#define AR_TIMER_MODE_SWBA 0x00000004
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#define AR_TIMER_MODE_HCF 0x00000008
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#define AR_TIMER_MODE_TIM 0x00000010
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#define AR_TIMER_MODE_DTIM 0x00000020
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#define AR_TIMER_MODE_QUIET 0x00000040
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#define AR_TIMER_MODE_NDP 0x00000080
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#define AR_TIMER_MODE_OVERFLOW_INDEX 0x00000700
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#define AR_TIMER_MODE_OVERFLOW_INDEX_S 8
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#define AR_TIMER_MODE_THRESH 0xFFFFF000
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#define AR_TIMER_MODE_THRESH_S 12
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/* PCU Misc modes */
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#define AR_PCU_FORCE_BSSID_MATCH 0x00000001 /* force bssid to match */
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#define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 /* tx/rx mic keys together */
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#define AR_PCU_TX_ADD_TSF 0x00000008 /* add tx_tsf + int_tsf */
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#define AR_PCU_CCK_SIFS_MODE 0x00000010 /* assume 11b sifs */
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#define AR_PCU_RX_ANT_UPDT 0x00000800 /* KC_RX_ANT_UPDATE */
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#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 /* enforce txop / tbtt */
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#define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 /* count bmiss's when sleeping */
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#define AR_PCU_BUG_12306_FIX_ENA 0x00020000 /* use rx_clear to count sifs */
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#define AR_PCU_FORCE_QUIET_COLL 0x00040000 /* kill xmit for channel change */
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#define AR_PCU_TBTT_PROTECT 0x00200000 /* no xmit upto tbtt+20 uS */
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#define AR_PCU_CLEAR_VMF 0x01000000 /* clear vmf mode (fast cc)*/
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#define AR_PCU_CLEAR_BA_VALID 0x04000000 /* clear ba state */
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/* GPIO Interrupt */
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#define AR_INTR_GPIO 0x3FF00000 /* gpio interrupted */
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#define AR_INTR_GPIO_S 20
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#define AR_GPIO_OUT_CTRL 0x000003FF /* 0 = out, 1 = in */
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#define AR_GPIO_OUT_VAL 0x000FFC00
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#define AR_GPIO_OUT_VAL_S 10
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#define AR_GPIO_INTR_CTRL 0x3FF00000
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#define AR_GPIO_INTR_CTRL_S 20
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#define AR_2040_JOINED_RX_CLEAR 0x00000001 /* use ctl + ext rx_clear for cca */
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#define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF
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#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700
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/* Eeprom defines */
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#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff
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#define AR_EEPROM_STATUS_DATA_VAL_S 0
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#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000
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#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000
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#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000
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#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000
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#define AR_SREV_REVISION_OWL_10 0x08
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#define AR_SREV_REVISION_OWL_20 0x09
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#define AR_SREV_REVISION_OWL_22 0x0a
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#define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */
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#define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */
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#define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */
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#define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */
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/* Test macro for owl 1.0 */
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#define IS_5416V1(_ah) ((_ah)->ah_macRev == AR_SREV_REVISION_OWL_10)
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#define IS_5416V2(_ah) ((_ah)->ah_macRev >= AR_SREV_REVISION_OWL_20)
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#define IS_5416V2_2(_ah) ((_ah)->ah_macRev == AR_SREV_REVISION_OWL_22)
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/* Expanded Mac Silicon Rev (16 bits starting with Sowl) */
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#define AR_XSREV_ID 0xFFFFFFFF /* Chip ID */
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#define AR_XSREV_ID_S 0
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#define AR_XSREV_VERSION 0xFFFC0000 /* Chip version */
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#define AR_XSREV_VERSION_S 18
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#define AR_XSREV_TYPE 0x0003F000 /* Chip type */
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#define AR_XSREV_TYPE_S 12
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#define AR_XSREV_TYPE_CHAIN 0x00001000 /* Chain Mode (1:3 chains,
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* 0:2 chains) */
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#define AR_XSREV_TYPE_HOST_MODE 0x00002000 /* Host Mode (1:PCI, 0:PCIe) */
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#define AR_XSREV_REVISION 0x00000F00
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#define AR_XSREV_REVISION_S 8
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#define AR_XSREV_VERSION_OWL_PCI 0x0D
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#define AR_XSREV_VERSION_OWL_PCIE 0x0C
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#define AR_XSREV_REVISION_OWL_10 0 /* Owl 1.0 */
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#define AR_XSREV_REVISION_OWL_20 1 /* Owl 2.0/2.1 */
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#define AR_XSREV_REVISION_OWL_22 2 /* Owl 2.2 */
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#define AR_XSREV_VERSION_SOWL 0x40
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#define AR_XSREV_REVISION_SOWL_10 0 /* Sowl 1.0 */
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#define AR_XSREV_REVISION_SOWL_11 1 /* Sowl 1.1 */
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#define AR_XSREV_VERSION_MERLIN 0x80 /* Merlin Version */
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#define AR_XSREV_REVISION_MERLIN_10 0 /* Merlin 1.0 */
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#define AR_XSREV_REVISION_MERLIN_20 1 /* Merlin 2.0 */
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#define AR_XSREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */
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#define AR_XSREV_VERSION_KITE 0xC0 /* Kite Version */
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#define AR_XSREV_REVISION_KITE_10 0 /* Kite 1.0 */
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#define AR_SREV_OWL_20_OR_LATER(_ah) \
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(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL || \
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AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_20)
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#define AR_SREV_OWL_22_OR_LATER(_ah) \
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(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL || \
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AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_22)
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#define AR_SREV_SOWL(_ah) \
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(AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_SOWL)
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#define AR_SREV_SOWL_10_OR_LATER(_ah) \
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(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL)
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#define AR_SREV_SOWL_11(_ah) \
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(AR_SREV_SOWL(_ah) && \
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AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_SOWL_11)
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#define AR_SREV_MERLIN(_ah) \
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(AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_MERLIN)
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#define AR_SREV_MERLIN_10_OR_LATER(_ah) \
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(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN)
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#define AR_SREV_MERLIN_20(_ah) \
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(AR_SREV_MERLIN(_ah) && \
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AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20)
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#define AR_SREV_MERLIN_20_OR_LATER(_ah) \
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(AR_SREV_MERLIN_20(_ah) || \
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AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_MERLIN)
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#define AR_SREV_KITE(_ah) \
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(AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE)
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#define AR_SREV_KITE_10_OR_LATER(_ah) \
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(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE)
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#endif /* _DEV_ATH_AR5416REG_H */
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