0aeed3e993
Freescale's QorIQ line includes a new ethernet controller, based on their Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame manager, Buffer manager, and Queue manager to improve performance across all interfaces by being able to pass data directly between hardware acceleration interfaces. As part of this import, Freescale's Netcomm Software (ncsw) driver is imported. This was an attempt by Freescale to create an OS-agnostic sub-driver for managing the hardware, using shims to interface to the OS-specific APIs. This work was abandoned, and Freescale's primary work is in the Linux driver (dual BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than going through the vendor area. Going forward, FreeBSD-specific changes may be made to the ncsw code, diverging from the upstream in potentially incompatible ways. An alternative could be to import the Linux driver itself, using the linuxKPI layer, as that would maintain parity with the vendor-maintained driver. However, the Linux driver has not been evaluated for reliability yet, and may have issues with the import, whereas the ncsw-based driver in this commit was completed by Semihalf 4 years ago, and is very stable. Other SoC modules based on DPAA, which could be added in the future: * Security and Encryption engine (SEC4.x, SEC5.x) * RAID engine Additional work to be done: * Implement polling mode * Test vlan support * Add support for the Pattern Matching Engine, which can do regular expression matching on packets. This driver has been tested on the P5020 QorIQ SoC. Others listed in the dtsec(4) manual page are expected to work as the same DPAA engine is included in all. Obtained from: Semihalf Relnotes: Yes Sponsored by: Alex Perez/Inertial Computing
155 lines
4.2 KiB
C
155 lines
4.2 KiB
C
/*-
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* Copyright (c) 2011-2012 Semihalf.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef IF_DTSEC_H_
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#define IF_DTSEC_H_
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/**
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* @group dTSEC common API.
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* @{
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*/
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#define DTSEC_MODE_REGULAR 0
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#define DTSEC_MODE_INDEPENDENT 1
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#define DTSEC_LOCK(sc) mtx_lock(&(sc)->sc_lock)
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#define DTSEC_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
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#define DTSEC_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
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#define DTSEC_MII_LOCK(sc) mtx_lock(&(sc)->sc_mii_lock)
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#define DTSEC_MII_UNLOCK(sc) mtx_unlock(&(sc)->sc_mii_lock)
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enum eth_dev_type {
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ETH_DTSEC = 0x1,
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ETH_10GSEC = 0x2
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};
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struct dtsec_softc {
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/* XXX MII bus requires that struct ifnet is first!!! */
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struct ifnet *sc_ifnet;
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device_t sc_dev;
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struct mtx sc_lock;
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int sc_mode;
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/* Methods */
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int (*sc_port_rx_init)
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(struct dtsec_softc *sc, int unit);
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int (*sc_port_tx_init)
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(struct dtsec_softc *sc, int unit);
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void (*sc_start_locked)
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(struct dtsec_softc *sc);
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/* dTSEC data */
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enum eth_dev_type sc_eth_dev_type;
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uint8_t sc_eth_id;
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uintptr_t sc_mac_mem_offset;
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e_EnetMode sc_mac_enet_mode;
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int sc_mac_mdio_irq;
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uint8_t sc_mac_addr[6];
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int sc_port_rx_hw_id;
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int sc_port_tx_hw_id;
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uint32_t sc_port_tx_qman_chan;
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int sc_phy_addr;
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bool sc_hidden;
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/* Params from fman_bus driver */
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vm_offset_t sc_fm_base;
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t_Handle sc_fmh;
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t_Handle sc_muramh;
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t_Handle sc_mach;
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t_Handle sc_rxph;
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t_Handle sc_txph;
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/* MII data */
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struct mii_data *sc_mii;
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device_t sc_mii_dev;
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struct mtx sc_mii_lock;
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struct callout sc_tick_callout;
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/* RX Pool */
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t_Handle sc_rx_pool;
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uint8_t sc_rx_bpid;
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uma_zone_t sc_rx_zone;
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char sc_rx_zname[64];
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/* RX Frame Queue */
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t_Handle sc_rx_fqr;
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uint32_t sc_rx_fqid;
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/* TX Frame Queue */
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t_Handle sc_tx_fqr;
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bool sc_tx_fqr_full;
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t_Handle sc_tx_conf_fqr;
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uint32_t sc_tx_conf_fqid;
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/* Frame Info Zone */
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uma_zone_t sc_fi_zone;
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char sc_fi_zname[64];
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};
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/** @} */
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/**
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* @group dTSEC FMan PORT API.
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* @{
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*/
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enum dtsec_fm_port_params {
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FM_PORT_LIODN_BASE = 0,
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FM_PORT_LIODN_OFFSET = 0,
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FM_PORT_MEM_ID = 0,
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FM_PORT_MEM_ATTR = MEMORY_ATTR_CACHEABLE,
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FM_PORT_BUFFER_SIZE = MCLBYTES,
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};
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e_FmPortType dtsec_fm_port_rx_type(enum eth_dev_type type);
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void dtsec_fm_port_rx_exception_callback(t_Handle app,
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e_FmPortExceptions exception);
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void dtsec_fm_port_tx_exception_callback(t_Handle app,
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e_FmPortExceptions exception);
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e_FmPortType dtsec_fm_port_tx_type(enum eth_dev_type type);
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/** @} */
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/**
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* @group dTSEC bus interface.
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* @{
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*/
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int dtsec_attach(device_t dev);
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int dtsec_detach(device_t dev);
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int dtsec_suspend(device_t dev);
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int dtsec_resume(device_t dev);
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int dtsec_shutdown(device_t dev);
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int dtsec_miibus_readreg(device_t dev, int phy, int reg);
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int dtsec_miibus_writereg(device_t dev, int phy, int reg,
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int value);
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void dtsec_miibus_statchg(device_t dev);
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/** @} */
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#endif /* IF_DTSEC_H_ */
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