35011d20cb
Features: - network driver for the four 10G interfaces and two management ports on XLP 8xx. - Support 4xx and 3xx variants of the processor. - Source code and firmware building for the 16 mips32r2 micro-code engines in the Network Accelerator. - Basic initialization code for Packet ordering Engine. Submitted by: Prabhath Raman (prabhath at netlogicmicro com) [refactored and fixed up for style by jchandra]
218 lines
9.3 KiB
C
218 lines
9.3 KiB
C
/*-
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __NLM_SGMII_H__
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#define __NLM_SGMII_H__
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/**
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* @file_name sgmii.h
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* @author Netlogic Microsystems
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* @brief Basic definitions of XLP SGMII ports
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*/
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#define SGMII_MAC_CONF1(block, i) NAE_REG(block, i, 0x00)
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#define SGMII_MAC_CONF2(block, i) NAE_REG(block, i, 0x01)
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#define SGMII_IPG_IFG(block, i) NAE_REG(block, i, 0x02)
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#define SGMII_HLF_DUP(block, i) NAE_REG(block, i, 0x03)
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#define SGMII_MAX_FRAME(block, i) NAE_REG(block, i, 0x04)
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#define SGMII_TEST(block, i) NAE_REG(block, i, 0x07)
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#define SGMII_MIIM_CONF(block, i) NAE_REG(block, i, 0x08)
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#define SGMII_MIIM_CMD(block, i) NAE_REG(block, i, 0x09)
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#define SGMII_MIIM_ADDR(block, i) NAE_REG(block, i, 0x0a)
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#define SGMII_MIIM_CTRL(block, i) NAE_REG(block, i, 0x0b)
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#define SGMII_MIIM_STAT(block, i) NAE_REG(block, i, 0x0c)
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#define SGMII_MIIM_IND(block, i) NAE_REG(block, i, 0x0d)
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#define SGMII_IO_CTRL(block, i) NAE_REG(block, i, 0x0e)
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#define SGMII_IO_STAT(block, i) NAE_REG(block, i, 0x0f)
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#define SGMII_STATS_MLR(block, i) NAE_REG(block, i, 0x1f)
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#define SGMII_STATS_TR64(block, i) NAE_REG(block, i, 0x20)
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#define SGMII_STATS_TR127(block, i) NAE_REG(block, i, 0x21)
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#define SGMII_STATS_TR255(block, i) NAE_REG(block, i, 0x22)
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#define SGMII_STATS_TR511(block, i) NAE_REG(block, i, 0x23)
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#define SGMII_STATS_TR1K(block, i) NAE_REG(block, i, 0x24)
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#define SGMII_STATS_TRMAX(block, i) NAE_REG(block, i, 0x25)
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#define SGMII_STATS_TRMGV(block, i) NAE_REG(block, i, 0x26)
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#define SGMII_STATS_RBYT(block, i) NAE_REG(block, i, 0x27)
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#define SGMII_STATS_RPKT(block, i) NAE_REG(block, i, 0x28)
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#define SGMII_STATS_RFCS(block, i) NAE_REG(block, i, 0x29)
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#define SGMII_STATS_RMCA(block, i) NAE_REG(block, i, 0x2a)
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#define SGMII_STATS_RBCA(block, i) NAE_REG(block, i, 0x2b)
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#define SGMII_STATS_RXCF(block, i) NAE_REG(block, i, 0x2c)
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#define SGMII_STATS_RXPF(block, i) NAE_REG(block, i, 0x2d)
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#define SGMII_STATS_RXUO(block, i) NAE_REG(block, i, 0x2e)
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#define SGMII_STATS_RALN(block, i) NAE_REG(block, i, 0x2f)
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#define SGMII_STATS_RFLR(block, i) NAE_REG(block, i, 0x30)
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#define SGMII_STATS_RCDE(block, i) NAE_REG(block, i, 0x31)
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#define SGMII_STATS_RCSE(block, i) NAE_REG(block, i, 0x32)
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#define SGMII_STATS_RUND(block, i) NAE_REG(block, i, 0x33)
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#define SGMII_STATS_ROVR(block, i) NAE_REG(block, i, 0x34)
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#define SGMII_STATS_RFRG(block, i) NAE_REG(block, i, 0x35)
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#define SGMII_STATS_RJBR(block, i) NAE_REG(block, i, 0x36)
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#define SGMII_STATS_TBYT(block, i) NAE_REG(block, i, 0x38)
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#define SGMII_STATS_TPKT(block, i) NAE_REG(block, i, 0x39)
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#define SGMII_STATS_TMCA(block, i) NAE_REG(block, i, 0x3a)
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#define SGMII_STATS_TBCA(block, i) NAE_REG(block, i, 0x3b)
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#define SGMII_STATS_TXPF(block, i) NAE_REG(block, i, 0x3c)
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#define SGMII_STATS_TDFR(block, i) NAE_REG(block, i, 0x3d)
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#define SGMII_STATS_TEDF(block, i) NAE_REG(block, i, 0x3e)
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#define SGMII_STATS_TSCL(block, i) NAE_REG(block, i, 0x3f)
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#define SGMII_STATS_TMCL(block, i) NAE_REG(block, i, 0x40)
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#define SGMII_STATS_TLCL(block, i) NAE_REG(block, i, 0x41)
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#define SGMII_STATS_TXCL(block, i) NAE_REG(block, i, 0x42)
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#define SGMII_STATS_TNCL(block, i) NAE_REG(block, i, 0x43)
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#define SGMII_STATS_TJBR(block, i) NAE_REG(block, i, 0x46)
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#define SGMII_STATS_TFCS(block, i) NAE_REG(block, i, 0x47)
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#define SGMII_STATS_TXCF(block, i) NAE_REG(block, i, 0x48)
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#define SGMII_STATS_TOVR(block, i) NAE_REG(block, i, 0x49)
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#define SGMII_STATS_TUND(block, i) NAE_REG(block, i, 0x4a)
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#define SGMII_STATS_TFRG(block, i) NAE_REG(block, i, 0x4b)
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#define SGMII_STATS_CAR1(block, i) NAE_REG(block, i, 0x4c)
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#define SGMII_STATS_CAR2(block, i) NAE_REG(block, i, 0x4d)
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#define SGMII_STATS_CAM1(block, i) NAE_REG(block, i, 0x4e)
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#define SGMII_STATS_CAM2(block, i) NAE_REG(block, i, 0x4f)
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#define SGMII_MAC_ADDR0_LO(block, i) NAE_REG(block, i, 0x50)
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#define SGMII_MAC_ADDR0_HI(block, i) NAE_REG(block, i, 0x51)
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#define SGMII_MAC_ADDR1_LO(block, i) NAE_REG(block, i, 0x52)
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#define SGMII_MAC_ADDR1_HI(block, i) NAE_REG(block, i, 0x53)
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#define SGMII_MAC_ADDR2_LO(block, i) NAE_REG(block, i, 0x54)
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#define SGMII_MAC_ADDR2_HI(block, i) NAE_REG(block, i, 0x55)
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#define SGMII_MAC_ADDR3_LO(block, i) NAE_REG(block, i, 0x56)
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#define SGMII_MAC_ADDR3_HI(block, i) NAE_REG(block, i, 0x57)
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#define SGMII_MAC_ADDR_MASK0_LO(block, i) NAE_REG(block, i, 0x58)
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#define SGMII_MAC_ADDR_MASK0_HI(block, i) NAE_REG(block, i, 0x59)
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#define SGMII_MAC_ADDR_MASK1_LO(block, i) NAE_REG(block, i, 0x5a)
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#define SGMII_MAC_ADDR_MASK1_HI(block, i) NAE_REG(block, i, 0x5b)
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#define SGMII_MAC_FILTER_CONFIG(block, i) NAE_REG(block, i, 0x5c)
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#define SGMII_HASHTBL_VEC_B31_0(block, i) NAE_REG(block, i, 0x60)
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#define SGMII_HASHTBL_VEC_B63_32(block, i) NAE_REG(block, i, 0x61)
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#define SGMII_HASHTBL_VEC_B95_64(block, i) NAE_REG(block, i, 0x62)
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#define SGMII_HASHTBL_VEC_B127_96(block, i) NAE_REG(block, i, 0x63)
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#define SGMII_HASHTBL_VEC_B159_128(block, i) NAE_REG(block, i, 0x64)
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#define SGMII_HASHTBL_VEC_B191_160(block, i) NAE_REG(block, i, 0x65)
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#define SGMII_HASHTBL_VEC_B223_192(block, i) NAE_REG(block, i, 0x66)
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#define SGMII_HASHTBL_VEC_B255_224(block, i) NAE_REG(block, i, 0x67)
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#define SGMII_HASHTBL_VEC_B287_256(block, i) NAE_REG(block, i, 0x68)
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#define SGMII_HASHTBL_VEC_B319_288(block, i) NAE_REG(block, i, 0x69)
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#define SGMII_HASHTBL_VEC_B351_320(block, i) NAE_REG(block, i, 0x6a)
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#define SGMII_HASHTBL_VEC_B383_352(block, i) NAE_REG(block, i, 0x6b)
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#define SGMII_HASHTBL_VEC_B415_384(block, i) NAE_REG(block, i, 0x6c)
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#define SGMII_HASHTBL_VEC_B447_416(block, i) NAE_REG(block, i, 0x6d)
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#define SGMII_HASHTBL_VEC_B479_448(block, i) NAE_REG(block, i, 0x6e)
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#define SGMII_HASHTBL_VEC_B511_480(block, i) NAE_REG(block, i, 0x6f)
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#define SGMII_NETIOR_VLANTYPE_FILTER(block, i) NAE_REG(block, i, 0x76)
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#define SGMII_NETIOR_RXDROP_CNTR(block, i) NAE_REG(block, i, 0x77)
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#define SGMII_NETIOR_PAUSE_QUANTAMULT(block, i) NAE_REG(block, i, 0x78)
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#define SGMII_NETIOR_MAC_CTRL_OPCODE(block, i) NAE_REG(block, i, 0x79)
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#define SGMII_NETIOR_MAC_DA_H(block, i) NAE_REG(block, i, 0x7a)
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#define SGMII_NETIOR_MAC_DA_L(block, i) NAE_REG(block, i, 0x7b)
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#define SGMII_NET_IFACE_CTRL3(block, i) NAE_REG(block, i, 0x7c)
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#define SGMII_NETIOR_GMAC_STAT(block, i) NAE_REG(block, i, 0x7d)
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#define SGMII_NET_IFACE_CTRL2(block, i) NAE_REG(block, i, 0x7e)
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#define SGMII_NET_IFACE_CTRL(block, i) NAE_REG(block, i, 0x7f)
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#if !defined(LOCORE) && !defined(__ASSEMBLY__)
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/* speed */
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enum nlm_sgmii_speed {
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NLM_SGMII_SPEED_10,
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NLM_SGMII_SPEED_100,
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NLM_SGMII_SPEED_1000,
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NLM_SGMII_SPEED_RSVD
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};
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/* duplexity */
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enum nlm_sgmii_duplex_mode {
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NLM_SGMII_DUPLEX_AUTO,
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NLM_SGMII_DUPLEX_HALF,
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NLM_SGMII_DUPLEX_FULL
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};
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/* stats */
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enum {
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nlm_sgmii_stats_mlr,
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nlm_sgmii_stats_tr64,
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nlm_sgmii_stats_tr127,
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nlm_sgmii_stats_tr255,
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nlm_sgmii_stats_tr511,
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nlm_sgmii_stats_tr1k,
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nlm_sgmii_stats_trmax,
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nlm_sgmii_stats_trmgv,
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nlm_sgmii_stats_rbyt,
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nlm_sgmii_stats_rpkt,
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nlm_sgmii_stats_rfcs,
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nlm_sgmii_stats_rmca,
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nlm_sgmii_stats_rbca,
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nlm_sgmii_stats_rxcf,
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nlm_sgmii_stats_rxpf,
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nlm_sgmii_stats_rxuo,
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nlm_sgmii_stats_raln,
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nlm_sgmii_stats_rflr,
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nlm_sgmii_stats_rcde,
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nlm_sgmii_stats_rcse,
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nlm_sgmii_stats_rund,
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nlm_sgmii_stats_rovr,
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nlm_sgmii_stats_rfrg,
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nlm_sgmii_stats_rjbr,
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nlm_sgmii_stats_rdummy, /* not used */
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nlm_sgmii_stats_tbyt,
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nlm_sgmii_stats_tpkt,
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nlm_sgmii_stats_tmca,
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nlm_sgmii_stats_tbca,
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nlm_sgmii_stats_txpf,
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nlm_sgmii_stats_tdfr,
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nlm_sgmii_stats_tedf,
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nlm_sgmii_stats_tscl,
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nlm_sgmii_stats_tmcl,
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nlm_sgmii_stats_tlcl,
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nlm_sgmii_stats_txcl,
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nlm_sgmii_stats_tncl,
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nlm_sgmii_stats_tjbr,
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nlm_sgmii_stats_tfcs,
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nlm_sgmii_stats_txcf,
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nlm_sgmii_stats_tovr,
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nlm_sgmii_stats_tund,
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nlm_sgmii_stats_tfrg,
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nlm_sgmii_stats_car1,
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nlm_sgmii_stats_car2,
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nlm_sgmii_stats_cam1,
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nlm_sgmii_stats_cam2
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};
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void nlm_configure_sgmii_interface(uint64_t, int, int, int, int);
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void nlm_sgmii_pcs_init(uint64_t, uint32_t);
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void nlm_nae_setup_mac(uint64_t, int, int, int, int, int, int, int);
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void nlm_nae_setup_rx_mode_sgmii(uint64_t, int, int, int, int, int,
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int, int);
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void nlm_nae_setup_mac_addr_sgmii(uint64_t, int, int, int, uint8_t *);
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#endif /* !(LOCORE) && !(__ASSEMBLY__) */
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#endif
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