320 lines
7.1 KiB
Plaintext
320 lines
7.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree for the ARM Integrator/CP platform
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*/
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/dts-v1/;
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/include/ "integrator.dtsi"
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/ {
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model = "ARM Integrator/CP";
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compatible = "arm,integrator-cp";
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chosen {
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bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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/*
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* Since the board has pluggable CPU modules, we
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* cannot define a proper compatible here. Let the
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* boot loader fill in the apropriate compatible
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* string if necessary.
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*/
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/* compatible = "arm,arm920t"; */
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reg = <0>;
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/*
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* TBD comment.
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*/
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/* kHz uV */
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operating-points = <50000 0
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48000 0>;
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clocks = <&cmcore>;
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clock-names = "cpu";
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clock-latency = <1000000>; /* 1 ms */
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};
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};
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/*
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* The Integrator/CP overall clocking architecture can be found in
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* ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which
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* appear to illustrate the layout used in most configurations.
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*/
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/* The codec chrystal operates at 24.576 MHz */
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xtal_codec: xtal24.576@24.576M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24576000>;
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};
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/* The chrystal is divided by 2 by the codec for the AACI bit clock */
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aaci_bitclk: aaci_bitclk@12.288M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <2>;
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clock-mult = <1>;
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clocks = <&xtal_codec>;
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};
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/* This is a 25MHz chrystal on the base board */
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xtal25mhz: xtal25mhz@25M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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/* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
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uartclk: uartclk@14.74M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <14745600>;
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};
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/* Actually sysclk I think */
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pclk: pclk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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core-module@10000000 {
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/* 24 MHz chrystal on the core module */
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cm24mhz: cm24mhz@24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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/* Oscillator on the core module, clocks the CPU core */
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cmcore: cmosc@24M {
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compatible = "arm,syscon-icst525-integratorcp-cm-core";
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#clock-cells = <0>;
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lock-offset = <0x14>;
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vco-offset = <0x08>;
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clocks = <&cm24mhz>;
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};
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/* Oscillator on the core module, clocks the memory bus */
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cmmem: cmosc@24M {
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compatible = "arm,syscon-icst525-integratorcp-cm-mem";
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#clock-cells = <0>;
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lock-offset = <0x14>;
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vco-offset = <0x08>;
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clocks = <&cm24mhz>;
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};
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/* Auxilary oscillator on the core module, clocks the CLCD */
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auxosc: auxosc@24M {
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compatible = "arm,syscon-icst525";
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#clock-cells = <0>;
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lock-offset = <0x14>;
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vco-offset = <0x1c>;
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clocks = <&cm24mhz>;
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};
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/* The KMI clock is the 24 MHz oscillator divided to 8MHz */
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kmiclk: kmiclk@1M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <3>;
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clock-mult = <1>;
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clocks = <&cm24mhz>;
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};
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/* The timer clock is the 24 MHz oscillator divided to 1MHz */
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timclk: timclk@1M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <24>;
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clock-mult = <1>;
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clocks = <&cm24mhz>;
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};
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};
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syscon {
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compatible = "arm,integrator-cp-syscon", "syscon";
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reg = <0xcb000000 0x100>;
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};
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timer0: timer@13000000 {
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/* TIMER0 runs directly on the 25MHz chrystal */
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compatible = "arm,integrator-cp-timer";
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clocks = <&xtal25mhz>;
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};
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timer1: timer@13000100 {
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/* TIMER1 runs @ 1MHz */
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compatible = "arm,integrator-cp-timer";
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clocks = <&timclk>;
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};
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timer2: timer@13000200 {
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/* TIMER2 runs @ 1MHz */
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compatible = "arm,integrator-cp-timer";
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clocks = <&timclk>;
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};
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pic: pic@14000000 {
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valid-mask = <0x1fc003ff>;
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};
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cic: cic@10000040 {
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compatible = "arm,versatile-fpga-irq";
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#interrupt-cells = <1>;
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interrupt-controller;
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reg = <0x10000040 0x100>;
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clear-mask = <0xffffffff>;
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valid-mask = <0x00000007>;
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};
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/* The SIC is cascaded off IRQ 26 on the PIC */
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sic: sic@ca000000 {
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compatible = "arm,versatile-fpga-irq";
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interrupt-parent = <&pic>;
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interrupts = <26>;
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#interrupt-cells = <1>;
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interrupt-controller;
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reg = <0xca000000 0x100>;
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clear-mask = <0x00000fff>;
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valid-mask = <0x00000fff>;
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};
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ethernet@c8000000 {
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compatible = "smsc,lan91c111";
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reg = <0xc8000000 0x10>;
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interrupt-parent = <&pic>;
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interrupts = <27>;
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};
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bridge {
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compatible = "ti,ths8134a", "ti,ths8134";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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vga_bridge_in: endpoint {
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remote-endpoint = <&clcd_pads_vga_dac>;
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};
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};
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port@1 {
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reg = <1>;
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vga_bridge_out: endpoint {
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remote-endpoint = <&vga_con_in>;
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};
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};
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};
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};
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vga {
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compatible = "vga-connector";
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port {
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vga_con_in: endpoint {
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remote-endpoint = <&vga_bridge_out>;
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};
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};
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};
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fpga {
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/*
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* These PrimeCells are at the same location and using
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* the same interrupts in all Integrators, but in the CP
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* slightly newer versions are deployed.
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*/
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rtc@15000000 {
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compatible = "arm,pl031", "arm,primecell";
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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uart@16000000 {
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compatible = "arm,pl011", "arm,primecell";
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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uart@17000000 {
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compatible = "arm,pl011", "arm,primecell";
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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kmi@18000000 {
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compatible = "arm,pl050", "arm,primecell";
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clocks = <&kmiclk>, <&pclk>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi@19000000 {
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compatible = "arm,pl050", "arm,primecell";
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clocks = <&kmiclk>, <&pclk>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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/*
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* These PrimeCells are only available on the Integrator/CP
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*/
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mmc@1c000000 {
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compatible = "arm,pl180", "arm,primecell";
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reg = <0x1c000000 0x1000>;
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interrupts = <23 24>;
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max-frequency = <515633>;
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clocks = <&uartclk>, <&pclk>;
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clock-names = "mclk", "apb_pclk";
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};
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aaci@1d000000 {
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compatible = "arm,pl041", "arm,primecell";
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reg = <0x1d000000 0x1000>;
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interrupts = <25>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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clcd@c0000000 {
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compatible = "arm,pl110", "arm,primecell";
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reg = <0xC0000000 0x1000>;
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interrupts = <22>;
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clocks = <&auxosc>, <&pclk>;
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clock-names = "clcdclk", "apb_pclk";
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/* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
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max-memory-bandwidth = <40000000>;
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/*
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* This port is routed through a PLD (Programmable
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* Logic Device) that routes the output from the CLCD
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* (after transformations) to the VGA DAC and also an
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* external panel connector. The PLD is essential for
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* supporting RGB565/BGR565.
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*
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* The signals from the port thus reaches two endpoints.
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* The PLD is managed through a few special bits in the
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* FPGA "sysreg".
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*
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* This arrangement can be clearly seen in
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* ARM DUI 0225D, page 3-41, figure 3-19.
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*/
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port@0 {
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clcd_pads_vga_dac: endpoint {
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remote-endpoint = <&vga_bridge_in>;
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arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
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};
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};
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};
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};
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};
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