473 lines
16 KiB
Plaintext
473 lines
16 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Google Veyron Jerry Rev 3+ board device tree source
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*
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* Copyright 2015 Google, Inc
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*/
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/dts-v1/;
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#include "rk3288-veyron-chromebook.dtsi"
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#include "cros-ec-sbs.dtsi"
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/ {
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model = "Google Jerry";
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compatible = "google,veyron-jerry-rev15", "google,veyron-jerry-rev14",
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"google,veyron-jerry-rev13", "google,veyron-jerry-rev12",
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"google,veyron-jerry-rev11", "google,veyron-jerry-rev10",
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"google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
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"google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
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"google,veyron-jerry-rev3", "google,veyron-jerry",
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"google,veyron", "rockchip,rk3288";
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};
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&rk808 {
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
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dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
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<&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
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regulators {
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mic_vcc: LDO_REG2 {
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regulator-name = "mic_vcc";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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};
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};
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&sdio0 {
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#address-cells = <1>;
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#size-cells = <0>;
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mwifiex: wifi@1 {
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compatible = "marvell,sd8897";
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reg = <1>;
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marvell,caldata-txpwrlimit-2g = /bits/ 8 <
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0x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01
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0x24 0x00 0x67 0x09 0x14 0x01 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
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0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
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0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x02 0x00 0x0f
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0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
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0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
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0x24 0x00 0x67 0x09 0x14 0x03 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
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0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
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0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x04 0x00 0x0f
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0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
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0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
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0x24 0x00 0x67 0x09 0x14 0x05 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
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0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
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0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x06 0x00 0x0f
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0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
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0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
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0x24 0x00 0x67 0x09 0x14 0x07 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
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0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
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0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x08 0x00 0x0f
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0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
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0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
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0x24 0x00 0x67 0x09 0x14 0x09 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
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0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
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0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0a 0x00 0x0f
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0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
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0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
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0x24 0x00 0x67 0x09 0x14 0x0b 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
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0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
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0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0c 0x00 0x0f
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0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
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0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
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0x24 0x00 0x67 0x09 0x14 0x0d 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
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0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
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0x0d 0x09 0x0e 0x09 0x0f 0x09>;
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marvell,caldata-txpwrlimit-5g-sub0 = /bits/ 8 <
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0x01 0x00 0x06 0x00 0xf0 0x01 0x89 0x01
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0x3a 0x00 0x88 0x13 0x14 0x24 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a
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0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09
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0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
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0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
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0x88 0x13 0x14 0x28 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a
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0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09
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0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05
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0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
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0x14 0x2c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09
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0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09
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0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05
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0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x30
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0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09
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0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05
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0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05
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0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x34 0x01 0x0c
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0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09
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0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05
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0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05
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0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x38 0x01 0x0c 0x02 0x0c
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0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a
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0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05
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0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05
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0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x3c 0x01 0x0c 0x02 0x0c 0x03 0x0c
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0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a
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0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05
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0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05
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0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x40 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a
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0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a
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0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05
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0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>;
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marvell,caldata-txpwrlimit-5g-sub1 = /bits/ 8 <
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0x01 0x00 0x06 0x00 0xaa 0x02 0x89 0x01
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0x3a 0x00 0x88 0x13 0x14 0x64 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a
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0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09
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0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
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0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
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0x88 0x13 0x14 0x68 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a
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0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09
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0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05
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0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
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0x14 0x6c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09
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0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09
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0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05
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0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x70
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0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09
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0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05
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0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05
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0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x74 0x01 0x0c
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0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09
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0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05
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0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05
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0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x78 0x01 0x0c 0x02 0x0c
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0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a
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0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05
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0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05
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0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x7c 0x01 0x0c 0x02 0x0c 0x03 0x0c
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0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a
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0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05
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0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05
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0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x80 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a
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0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a
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0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05
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0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01
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0x3a 0x00 0x88 0x13 0x14 0x84 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a
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0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09
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0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
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0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
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0x88 0x13 0x14 0x88 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a
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0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08
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0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04
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0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
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0x14 0x8c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08
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0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08
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0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04
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0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>;
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marvell,caldata-txpwrlimit-5g-sub2 = /bits/ 8 <
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0x01 0x00 0x06 0x00 0x36 0x01 0x89 0x01
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0x3a 0x00 0x88 0x13 0x14 0x95 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a
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0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08
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0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
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0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
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0x88 0x13 0x14 0x99 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a
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0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08
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0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04
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0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
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0x14 0x9d 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08
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|
0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08
|
|
0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04
|
|
0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa1
|
|
0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08
|
|
0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04
|
|
0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05
|
|
0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa5 0x01 0x0b
|
|
0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08
|
|
0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04
|
|
0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05
|
|
0x1a 0x05 0x1b 0x05>;
|
|
};
|
|
};
|
|
|
|
&sdmmc {
|
|
disable-wp;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
|
|
&sdmmc_bus4>;
|
|
};
|
|
|
|
&vcc_5v {
|
|
enable-active-high;
|
|
gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&drv_5v>;
|
|
};
|
|
|
|
&vcc50_hdmi {
|
|
enable-active-high;
|
|
gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&vcc50_hdmi_en>;
|
|
};
|
|
|
|
&gpio0 {
|
|
gpio-line-names = "PMIC_SLEEP_AP",
|
|
"DDRIO_PWROFF",
|
|
"DDRIO_RETEN",
|
|
"TS3A227E_INT_L",
|
|
"PMIC_INT_L",
|
|
"PWR_KEY_L",
|
|
"AP_LID_INT_L",
|
|
"EC_IN_RW",
|
|
|
|
"AC_PRESENT_AP",
|
|
/*
|
|
* RECOVERY_SW_L is Chrome OS ABI. Schematics call
|
|
* it REC_MODE_L.
|
|
*/
|
|
"RECOVERY_SW_L",
|
|
"OTP_OUT",
|
|
"HOST1_PWR_EN",
|
|
"USBOTG_PWREN_H",
|
|
"AP_WARM_RESET_H",
|
|
"nFAULT2",
|
|
"I2C0_SDA_PMIC",
|
|
|
|
"I2C0_SCL_PMIC",
|
|
"SUSPEND_L",
|
|
"USB_INT";
|
|
};
|
|
|
|
&gpio2 {
|
|
gpio-line-names = "CONFIG0",
|
|
"CONFIG1",
|
|
"CONFIG2",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"CONFIG3",
|
|
|
|
"",
|
|
"EMMC_RST_L",
|
|
"",
|
|
"",
|
|
"BL_PWR_EN",
|
|
"AVDD_1V8_DISP_EN";
|
|
};
|
|
|
|
&gpio3 {
|
|
gpio-line-names = "FLASH0_D0",
|
|
"FLASH0_D1",
|
|
"FLASH0_D2",
|
|
"FLASH0_D3",
|
|
"FLASH0_D4",
|
|
"FLASH0_D5",
|
|
"FLASH0_D6",
|
|
"FLASH0_D7",
|
|
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
|
|
"FLASH0_CS2/EMMC_CMD",
|
|
"",
|
|
"FLASH0_DQS/EMMC_CLKO";
|
|
};
|
|
|
|
&gpio4 {
|
|
gpio-line-names = "",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
|
|
"UART0_RXD",
|
|
"UART0_TXD",
|
|
"UART0_CTS",
|
|
"UART0_RTS",
|
|
"SDIO0_D0",
|
|
"SDIO0_D1",
|
|
"SDIO0_D2",
|
|
"SDIO0_D3",
|
|
|
|
"SDIO0_CMD",
|
|
"SDIO0_CLK",
|
|
"BT_DEV_WAKE",
|
|
"",
|
|
"WIFI_ENABLE_H",
|
|
"BT_ENABLE_L",
|
|
"WIFI_HOST_WAKE",
|
|
"BT_HOST_WAKE";
|
|
};
|
|
|
|
&gpio5 {
|
|
gpio-line-names = "",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
"SPI0_CLK",
|
|
"SPI0_CS0",
|
|
"SPI0_TXD",
|
|
"SPI0_RXD",
|
|
|
|
"",
|
|
"",
|
|
"",
|
|
"VCC50_HDMI_EN";
|
|
};
|
|
|
|
&gpio6 {
|
|
gpio-line-names = "I2S0_SCLK",
|
|
"I2S0_LRCK_RX",
|
|
"I2S0_LRCK_TX",
|
|
"I2S0_SDI",
|
|
"I2S0_SDO0",
|
|
"HP_DET_H",
|
|
"",
|
|
"INT_CODEC",
|
|
|
|
"I2S0_CLK",
|
|
"I2C2_SDA",
|
|
"I2C2_SCL",
|
|
"MICDET",
|
|
"",
|
|
"",
|
|
"",
|
|
"",
|
|
|
|
"SDMMC_D0",
|
|
"SDMMC_D1",
|
|
"SDMMC_D2",
|
|
"SDMMC_D3",
|
|
"SDMMC_CLK",
|
|
"SDMMC_CMD";
|
|
};
|
|
|
|
&gpio7 {
|
|
gpio-line-names = "LCDC_BL",
|
|
"PWM_LOG",
|
|
"BL_EN",
|
|
"TRACKPAD_INT",
|
|
"TPM_INT_H",
|
|
"SDMMC_DET_L",
|
|
/*
|
|
* AP_FLASH_WP_L is Chrome OS ABI. Schematics call
|
|
* it FW_WP_AP.
|
|
*/
|
|
"AP_FLASH_WP_L",
|
|
"EC_INT",
|
|
|
|
"CPU_NMI",
|
|
"DVSOK",
|
|
"",
|
|
"EDP_HPD",
|
|
"DVS1",
|
|
"nFAULT1",
|
|
"LCD_EN",
|
|
"DVS2",
|
|
|
|
"VCC5V_GOOD_H",
|
|
"I2C4_SDA_TP",
|
|
"I2C4_SCL_TP",
|
|
"I2C5_SDA_HDMI",
|
|
"I2C5_SCL_HDMI",
|
|
"5V_DRV",
|
|
"UART2_RXD",
|
|
"UART2_TXD";
|
|
};
|
|
|
|
&gpio8 {
|
|
gpio-line-names = "RAM_ID0",
|
|
"RAM_ID1",
|
|
"RAM_ID2",
|
|
"RAM_ID3",
|
|
"I2C1_SDA_TPM",
|
|
"I2C1_SCL_TPM",
|
|
"SPI2_CLK",
|
|
"SPI2_CS0",
|
|
|
|
"SPI2_RXD",
|
|
"SPI2_TXD";
|
|
};
|
|
|
|
&pinctrl {
|
|
buck-5v {
|
|
drv_5v: drv-5v {
|
|
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
hdmi {
|
|
vcc50_hdmi_en: vcc50-hdmi-en {
|
|
rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pmic {
|
|
dvs_1: dvs-1 {
|
|
rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
};
|
|
|
|
dvs_2: dvs-2 {
|
|
rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c4 {
|
|
status = "okay";
|
|
|
|
/*
|
|
* Trackpad pin control is shared between Elan and Synaptics devices
|
|
* so we have to pull it up to the bus level.
|
|
*/
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4_xfer &trackpad_int>;
|
|
|
|
trackpad@15 {
|
|
/*
|
|
* Remove the inherited pinctrl settings to avoid clashing
|
|
* with bus-wide ones.
|
|
*/
|
|
/delete-property/pinctrl-names;
|
|
/delete-property/pinctrl-0;
|
|
};
|
|
|
|
trackpad@2c {
|
|
compatible = "hid-over-i2c";
|
|
interrupt-parent = <&gpio7>;
|
|
interrupts = <RK_PA3 IRQ_TYPE_EDGE_FALLING>;
|
|
reg = <0x2c>;
|
|
hid-descr-addr = <0x0020>;
|
|
vcc-supply = <&vcc33_io>;
|
|
wakeup-source;
|
|
};
|
|
};
|