37da2ff61a
determined at runtime so there's no need to set the values in each DTS. Tested on YYHD18 (aml8726-m3), VSATV102 (aml8726-m6), and ODROIDC1 (aml8726-m8b). Differential Revision: https://reviews.freebsd.org/D2588 Submitted by: John Wehle
491 lines
11 KiB
C
491 lines
11 KiB
C
/*-
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* Copyright 2013-2015 John Wehle <john@feith.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Amlogic aml8726 RTC driver.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/clock.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/time.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/amlogic/aml8726/aml8726_soc.h>
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#include "clock_if.h"
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/*
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* The RTC initialization various slightly between the different chips.
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*
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* aml8726-m1 aml8726-m3 aml8726-m6 (and later)
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* init-always true true false
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* xo-init 0x0004 0x3c0a 0x180a
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* gpo-init 0x100000 0x100000 0x500000
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*/
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struct aml8726_rtc_init {
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boolean_t always;
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uint16_t xo;
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uint32_t gpo;
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};
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struct aml8726_rtc_softc {
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device_t dev;
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struct aml8726_rtc_init init;
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struct resource * res[2];
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struct mtx mtx;
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};
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static struct resource_spec aml8726_rtc_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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#define AML_RTC_LOCK(sc) mtx_lock_spin(&(sc)->mtx)
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#define AML_RTC_UNLOCK(sc) mtx_unlock_spin(&(sc)->mtx)
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#define AML_RTC_LOCK_INIT(sc) \
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mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
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"rtc", MTX_SPIN)
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#define AML_RTC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx);
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#define AML_RTC_0_REG 0
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#define AML_RTC_SCLK (1 << 0)
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#define AML_RTC_SDI (1 << 2)
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#define AML_RTC_SEN (1 << 1)
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#define AML_RTC_AS (1 << 17)
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#define AML_RTC_ABSY (1 << 22)
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#define AML_RTC_IRQ_DIS (1 << 12)
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#define AML_RTC_1_REG 4
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#define AML_RTC_SDO (1 << 0)
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#define AML_RTC_SRDY (1 << 1)
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#define AML_RTC_2_REG 8
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#define AML_RTC_3_REG 12
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#define AML_RTC_MSR_BUSY (1 << 20)
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#define AML_RTC_MSR_CA (1 << 17)
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#define AML_RTC_MSR_DURATION_EN (1 << 16)
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#define AML_RTC_MSR_DURATION_MASK 0xffff
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#define AML_RTC_MSR_DURATION_SHIFT 0
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#define AML_RTC_4_REG 16
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#define AML_RTC_TIME_SREG 0
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#define AML_RTC_GPO_SREG 1
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#define AML_RTC_GPO_LEVEL (1 << 24)
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#define AML_RTC_GPO_BUSY (1 << 23)
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#define AML_RTC_GPO_ACTIVE_HIGH (1 << 22)
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#define AML_RTC_GPO_CMD_MASK (3 << 20)
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#define AML_RTC_GPO_CMD_SHIFT 20
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#define AML_RTC_GPO_CMD_NOW (1 << 20)
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#define AML_RTC_GPO_CMD_COUNT (2 << 20)
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#define AML_RTC_GPO_CMD_PULSE (3 << 20)
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#define AML_RTC_GPO_CNT_MASK 0xfffff
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#define AML_RTC_GPO_CNT_SHIFT 0
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#define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val))
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#define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg)
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#define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \
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(BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE))
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static int
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aml8726_rtc_start_transfer(struct aml8726_rtc_softc *sc)
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{
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unsigned i;
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/* idle the serial interface */
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CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) &
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~(AML_RTC_SCLK | AML_RTC_SEN | AML_RTC_SDI)));
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CSR_BARRIER(sc, AML_RTC_0_REG);
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/* see if it is ready for a new cycle */
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for (i = 40; i; i--) {
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DELAY(5);
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if ( (CSR_READ_4(sc, AML_RTC_1_REG) & AML_RTC_SRDY) )
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break;
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}
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if (i == 0)
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return (EIO);
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/* start the cycle */
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CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) |
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AML_RTC_SEN));
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return (0);
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}
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static inline void
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aml8726_rtc_sclk_pulse(struct aml8726_rtc_softc *sc)
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{
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DELAY(5);
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CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) |
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AML_RTC_SCLK));
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CSR_BARRIER(sc, AML_RTC_0_REG);
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DELAY(5);
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CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) &
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~AML_RTC_SCLK));
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CSR_BARRIER(sc, AML_RTC_0_REG);
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}
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static inline void
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aml8726_rtc_send_bit(struct aml8726_rtc_softc *sc, unsigned bit)
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{
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if (bit) {
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CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) |
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AML_RTC_SDI));
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} else {
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CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) &
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~AML_RTC_SDI));
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}
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aml8726_rtc_sclk_pulse(sc);
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}
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static inline void
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aml8726_rtc_send_addr(struct aml8726_rtc_softc *sc, u_char addr)
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{
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unsigned mask;
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for (mask = 1 << 3; mask; mask >>= 1) {
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if (mask == 1) {
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/* final bit indicates read / write mode */
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CSR_WRITE_4(sc, AML_RTC_0_REG,
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(CSR_READ_4(sc, AML_RTC_0_REG) & ~AML_RTC_SEN));
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}
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aml8726_rtc_send_bit(sc, (addr & mask));
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}
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}
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static inline void
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aml8726_rtc_send_data(struct aml8726_rtc_softc *sc, uint32_t data)
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{
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unsigned mask;
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for (mask = 1U << 31; mask; mask >>= 1)
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aml8726_rtc_send_bit(sc, (data & mask));
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}
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static inline void
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aml8726_rtc_recv_data(struct aml8726_rtc_softc *sc, uint32_t *dp)
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{
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uint32_t data;
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unsigned i;
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data = 0;
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for (i = 0; i < 32; i++) {
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aml8726_rtc_sclk_pulse(sc);
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data <<= 1;
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data |= (CSR_READ_4(sc, AML_RTC_1_REG) & AML_RTC_SDO) ? 1 : 0;
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}
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*dp = data;
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}
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static int
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aml8726_rtc_sreg_read(struct aml8726_rtc_softc *sc, u_char sreg, uint32_t *val)
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{
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u_char addr;
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int error;
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/* read is indicated by lsb = 0 */
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addr = (sreg << 1) | 0;
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error = aml8726_rtc_start_transfer(sc);
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if (error)
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return (error);
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aml8726_rtc_send_addr(sc, addr);
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aml8726_rtc_recv_data(sc, val);
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return (0);
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}
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static int
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aml8726_rtc_sreg_write(struct aml8726_rtc_softc *sc, u_char sreg, uint32_t val)
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{
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u_char addr;
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int error;
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/* write is indicated by lsb = 1 */
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addr = (sreg << 1) | 1;
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error = aml8726_rtc_start_transfer(sc);
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if (error)
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return (error);
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aml8726_rtc_send_data(sc, val);
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aml8726_rtc_send_addr(sc, addr);
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return (0);
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}
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static int
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aml8726_rtc_initialize(struct aml8726_rtc_softc *sc)
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{
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int error;
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unsigned i;
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/* idle the serial interface */
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CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) &
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~(AML_RTC_SCLK | AML_RTC_SEN | AML_RTC_SDI)));
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CSR_BARRIER(sc, AML_RTC_0_REG);
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/* see if it is ready for a new cycle */
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for (i = 40; i; i--) {
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DELAY(5);
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if ( (CSR_READ_4(sc, AML_RTC_1_REG) & AML_RTC_SRDY) )
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break;
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}
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if (sc->init.always == TRUE || (CSR_READ_4(sc, AML_RTC_1_REG) &
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AML_RTC_SRDY) == 0) {
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/*
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* The RTC has a 16 bit initialization register. The upper
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* bits can be written directly. The lower bits are written
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* through a shift register.
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*/
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CSR_WRITE_4(sc, AML_RTC_4_REG, ((sc->init.xo >> 8) & 0xff));
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CSR_WRITE_4(sc, AML_RTC_0_REG,
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((CSR_READ_4(sc, AML_RTC_0_REG) & 0xffffff) |
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((uint32_t)(sc->init.xo & 0xff) << 24) | AML_RTC_AS |
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AML_RTC_IRQ_DIS));
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while ((CSR_READ_4(sc, AML_RTC_0_REG) & AML_RTC_ABSY) != 0)
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cpu_spinwait();
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DELAY(2);
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error = aml8726_rtc_sreg_write(sc, AML_RTC_GPO_SREG,
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sc->init.gpo);
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if (error)
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return (error);
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}
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return (0);
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}
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static int
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aml8726_rtc_check_xo(struct aml8726_rtc_softc *sc)
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{
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uint32_t now, previous;
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int i;
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/*
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* The RTC is driven by a 32.768khz clock meaning it's period
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* is roughly 30.5 us. Check that it's working (implying the
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* RTC could contain a valid value) by enabling count always
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* and seeing if the value changes after 200 us (per RTC User
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* Guide ... presumably the extra time is to cover XO startup).
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*/
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CSR_WRITE_4(sc, AML_RTC_3_REG, (CSR_READ_4(sc, AML_RTC_3_REG) |
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AML_RTC_MSR_CA));
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previous = CSR_READ_4(sc, AML_RTC_2_REG);
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for (i = 0; i < 4; i++) {
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DELAY(50);
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now = CSR_READ_4(sc, AML_RTC_2_REG);
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if (now != previous)
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break;
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}
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CSR_WRITE_4(sc, AML_RTC_3_REG, (CSR_READ_4(sc, AML_RTC_3_REG) &
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~AML_RTC_MSR_CA));
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if (now == previous)
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return (EINVAL);
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return (0);
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}
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static int
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aml8726_rtc_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "amlogic,aml8726-rtc"))
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return (ENXIO);
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device_set_desc(dev, "Amlogic aml8726 RTC");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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aml8726_rtc_attach(device_t dev)
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{
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struct aml8726_rtc_softc *sc = device_get_softc(dev);
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sc->dev = dev;
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switch (aml8726_soc_hw_rev) {
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case AML_SOC_HW_REV_M3:
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sc->init.always = true;
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sc->init.xo = 0x3c0a;
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sc->init.gpo = 0x100000;
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break;
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case AML_SOC_HW_REV_M6:
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case AML_SOC_HW_REV_M8:
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case AML_SOC_HW_REV_M8B:
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sc->init.always = false;
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sc->init.xo = 0x180a;
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sc->init.gpo = 0x500000;
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break;
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default:
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device_printf(dev, "unsupported SoC\n");
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return (ENXIO);
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/* NOTREACHED */
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}
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if (bus_alloc_resources(dev, aml8726_rtc_spec, sc->res)) {
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device_printf(dev, "can not allocate resources for device\n");
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return (ENXIO);
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}
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aml8726_rtc_initialize(sc);
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if (aml8726_rtc_check_xo(sc) != 0) {
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device_printf(dev, "crystal oscillator check failed\n");
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bus_release_resources(dev, aml8726_rtc_spec, sc->res);
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return (ENXIO);
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}
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AML_RTC_LOCK_INIT(sc);
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clock_register(dev, 1000000);
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return (0);
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}
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static int
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aml8726_rtc_detach(device_t dev)
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{
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return (EBUSY);
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}
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static int
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aml8726_rtc_gettime(device_t dev, struct timespec *ts)
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{
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struct aml8726_rtc_softc *sc = device_get_softc(dev);
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uint32_t sec;
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int error;
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AML_RTC_LOCK(sc);
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error = aml8726_rtc_sreg_read(sc, AML_RTC_TIME_SREG, &sec);
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AML_RTC_UNLOCK(sc);
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ts->tv_sec = sec;
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ts->tv_nsec = 0;
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return (error);
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}
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static int
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aml8726_rtc_settime(device_t dev, struct timespec *ts)
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{
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struct aml8726_rtc_softc *sc = device_get_softc(dev);
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uint32_t sec;
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int error;
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sec = ts->tv_sec;
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/* Accuracy is only one second. */
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if (ts->tv_nsec >= 500000000)
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sec++;
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AML_RTC_LOCK(sc);
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error = aml8726_rtc_sreg_write(sc, AML_RTC_TIME_SREG, sec);
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AML_RTC_UNLOCK(sc);
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return (error);
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}
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static device_method_t aml8726_rtc_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, aml8726_rtc_probe),
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DEVMETHOD(device_attach, aml8726_rtc_attach),
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DEVMETHOD(device_detach, aml8726_rtc_detach),
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/* Clock interface */
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DEVMETHOD(clock_gettime, aml8726_rtc_gettime),
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DEVMETHOD(clock_settime, aml8726_rtc_settime),
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DEVMETHOD_END
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};
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static driver_t aml8726_rtc_driver = {
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"rtc",
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aml8726_rtc_methods,
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sizeof(struct aml8726_rtc_softc),
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};
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static devclass_t aml8726_rtc_devclass;
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DRIVER_MODULE(rtc, simplebus, aml8726_rtc_driver, aml8726_rtc_devclass, 0, 0);
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