fdc5dd2d2f
Switch eventtimers(9) from using struct bintime to sbintime_t. Even before this not a single driver really supported full dynamic range of struct bintime even in theory, not speaking about practical inexpediency. This change legitimates the status quo and cleans up the code.
446 lines
11 KiB
C
446 lines
11 KiB
C
/*-
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* Copyright (c) 2006 Benno Rice.
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* Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
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* All rights reserved.
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*
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* Adapted to Marvell SoC by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/frame.h>
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#include <machine/intr.h>
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#include <arm/mv/mvreg.h>
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#include <arm/mv/mvvar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#define INITIAL_TIMECOUNTER (0xffffffff)
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#define MAX_WATCHDOG_TICKS (0xffffffff)
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#if defined(SOC_MV_ARMADAXP)
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#define MV_CLOCK_SRC get_l2clk()
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#else
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#define MV_CLOCK_SRC get_tclk()
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#endif
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struct mv_timer_softc {
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struct resource * timer_res[2];
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bus_space_tag_t timer_bst;
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bus_space_handle_t timer_bsh;
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struct mtx timer_mtx;
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struct eventtimer et;
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};
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static struct resource_spec mv_timer_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static struct mv_timer_softc *timer_softc = NULL;
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static int timers_initialized = 0;
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static int mv_timer_probe(device_t);
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static int mv_timer_attach(device_t);
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static int mv_hardclock(void *);
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static unsigned mv_timer_get_timecount(struct timecounter *);
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static uint32_t mv_get_timer_control(void);
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static void mv_set_timer_control(uint32_t);
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static uint32_t mv_get_timer(uint32_t);
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static void mv_set_timer(uint32_t, uint32_t);
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static void mv_set_timer_rel(uint32_t, uint32_t);
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static void mv_watchdog_enable(void);
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static void mv_watchdog_disable(void);
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static void mv_watchdog_event(void *, unsigned int, int *);
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static int mv_timer_start(struct eventtimer *et,
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sbintime_t first, sbintime_t period);
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static int mv_timer_stop(struct eventtimer *et);
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static void mv_setup_timers(void);
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static struct timecounter mv_timer_timecounter = {
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.tc_get_timecount = mv_timer_get_timecount,
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.tc_name = "CPUTimer1",
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.tc_frequency = 0, /* This is assigned on the fly in the init sequence */
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.tc_counter_mask = ~0u,
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.tc_quality = 1000,
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};
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static int
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mv_timer_probe(device_t dev)
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{
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if (!ofw_bus_is_compatible(dev, "mrvl,timer"))
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return (ENXIO);
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device_set_desc(dev, "Marvell CPU Timer");
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return (0);
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}
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static int
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mv_timer_attach(device_t dev)
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{
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int error;
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void *ihl;
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struct mv_timer_softc *sc;
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#if !defined(SOC_MV_ARMADAXP)
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uint32_t irq_cause, irq_mask;
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#endif
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if (timer_softc != NULL)
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return (ENXIO);
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sc = (struct mv_timer_softc *)device_get_softc(dev);
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timer_softc = sc;
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error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res);
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if (error) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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sc->timer_bst = rman_get_bustag(sc->timer_res[0]);
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sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]);
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mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF);
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mv_watchdog_disable();
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EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
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if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK,
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mv_hardclock, NULL, sc, &ihl) != 0) {
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bus_release_resources(dev, mv_timer_spec, sc->timer_res);
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device_printf(dev, "Could not setup interrupt.\n");
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return (ENXIO);
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}
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mv_setup_timers();
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#if !defined(SOC_MV_ARMADAXP)
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irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
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irq_cause &= IRQ_TIMER0_CLR;
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write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
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irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
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irq_mask |= IRQ_TIMER0_MASK;
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irq_mask &= ~IRQ_TIMER1_MASK;
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write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
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#endif
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sc->et.et_name = "CPUTimer0";
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sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
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sc->et.et_quality = 1000;
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sc->et.et_frequency = MV_CLOCK_SRC;
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sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
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sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
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sc->et.et_start = mv_timer_start;
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sc->et.et_stop = mv_timer_stop;
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sc->et.et_priv = sc;
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et_register(&sc->et);
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mv_timer_timecounter.tc_frequency = MV_CLOCK_SRC;
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tc_init(&mv_timer_timecounter);
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return (0);
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}
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static int
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mv_hardclock(void *arg)
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{
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struct mv_timer_softc *sc;
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uint32_t irq_cause;
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irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
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irq_cause &= IRQ_TIMER0_CLR;
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write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
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sc = (struct mv_timer_softc *)arg;
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if (sc->et.et_active)
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sc->et.et_event_cb(&sc->et, sc->et.et_arg);
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return (FILTER_HANDLED);
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}
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static device_method_t mv_timer_methods[] = {
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DEVMETHOD(device_probe, mv_timer_probe),
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DEVMETHOD(device_attach, mv_timer_attach),
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{ 0, 0 }
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};
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static driver_t mv_timer_driver = {
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"timer",
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mv_timer_methods,
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sizeof(struct mv_timer_softc),
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};
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static devclass_t mv_timer_devclass;
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DRIVER_MODULE(timer, simplebus, mv_timer_driver, mv_timer_devclass, 0, 0);
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static unsigned
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mv_timer_get_timecount(struct timecounter *tc)
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{
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return (INITIAL_TIMECOUNTER - mv_get_timer(1));
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}
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void
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cpu_initclocks(void)
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{
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cpu_initclocks_bsp();
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}
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void
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DELAY(int usec)
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{
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uint32_t val, val_temp;
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int32_t nticks;
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if (!timers_initialized) {
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for (; usec > 0; usec--)
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for (val = 100; val > 0; val--)
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__asm __volatile("nop" ::: "memory");
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return;
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}
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val = mv_get_timer(1);
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nticks = ((MV_CLOCK_SRC / 1000000 + 1) * usec);
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while (nticks > 0) {
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val_temp = mv_get_timer(1);
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if (val > val_temp)
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nticks -= (val - val_temp);
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else
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nticks -= (val + (INITIAL_TIMECOUNTER - val_temp));
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val = val_temp;
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}
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}
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static uint32_t
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mv_get_timer_control(void)
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{
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return (bus_space_read_4(timer_softc->timer_bst,
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timer_softc->timer_bsh, CPU_TIMER_CONTROL));
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}
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static void
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mv_set_timer_control(uint32_t val)
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{
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bus_space_write_4(timer_softc->timer_bst,
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timer_softc->timer_bsh, CPU_TIMER_CONTROL, val);
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}
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static uint32_t
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mv_get_timer(uint32_t timer)
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{
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return (bus_space_read_4(timer_softc->timer_bst,
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timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8));
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}
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static void
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mv_set_timer(uint32_t timer, uint32_t val)
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{
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bus_space_write_4(timer_softc->timer_bst,
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timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val);
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}
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static void
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mv_set_timer_rel(uint32_t timer, uint32_t val)
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{
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bus_space_write_4(timer_softc->timer_bst,
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timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val);
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}
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static void
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mv_watchdog_enable(void)
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{
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uint32_t val, irq_cause;
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#if !defined(SOC_MV_ARMADAXP)
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uint32_t irq_mask;
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#endif
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irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
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irq_cause &= IRQ_TIMER_WD_CLR;
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write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
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#if defined(SOC_MV_ARMADAXP)
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val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
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val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
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write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
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#else
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irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
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irq_mask |= IRQ_TIMER_WD_MASK;
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write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
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val = read_cpu_ctrl(RSTOUTn_MASK);
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val |= WD_RST_OUT_EN;
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write_cpu_ctrl(RSTOUTn_MASK, val);
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#endif
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val = mv_get_timer_control();
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val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO;
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mv_set_timer_control(val);
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}
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static void
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mv_watchdog_disable(void)
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{
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uint32_t val, irq_cause;
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#if !defined(SOC_MV_ARMADAXP)
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uint32_t irq_mask;
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#endif
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val = mv_get_timer_control();
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val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
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mv_set_timer_control(val);
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#if defined(SOC_MV_ARMADAXP)
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val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
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val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
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write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
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#else
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val = read_cpu_ctrl(RSTOUTn_MASK);
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val &= ~WD_RST_OUT_EN;
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write_cpu_ctrl(RSTOUTn_MASK, val);
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irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
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irq_mask &= ~(IRQ_TIMER_WD_MASK);
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write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
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#endif
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irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
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irq_cause &= IRQ_TIMER_WD_CLR;
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write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
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}
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/*
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* Watchdog event handler.
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*/
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static void
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mv_watchdog_event(void *arg, unsigned int cmd, int *error)
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{
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uint64_t ns;
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uint64_t ticks;
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mtx_lock(&timer_softc->timer_mtx);
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if (cmd == 0)
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mv_watchdog_disable();
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else {
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/*
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* Watchdog timeout is in nanosecs, calculation according to
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* watchdog(9)
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*/
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ns = (uint64_t)1 << (cmd & WD_INTERVAL);
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ticks = (uint64_t)(ns * MV_CLOCK_SRC) / 1000000000;
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if (ticks > MAX_WATCHDOG_TICKS)
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mv_watchdog_disable();
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else {
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/* Timer 2 is the watchdog */
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mv_set_timer(2, ticks);
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mv_watchdog_enable();
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*error = 0;
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}
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}
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mtx_unlock(&timer_softc->timer_mtx);
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}
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static int
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mv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
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{
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struct mv_timer_softc *sc;
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uint32_t val, val1;
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/* Calculate dividers. */
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sc = (struct mv_timer_softc *)et->et_priv;
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if (period != 0)
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val = ((uint32_t)sc->et.et_frequency * period) >> 32;
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else
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val = 0;
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if (first != 0)
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val1 = ((uint32_t)sc->et.et_frequency * first) >> 32;
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else
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val1 = val;
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/* Apply configuration. */
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mv_set_timer_rel(0, val);
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mv_set_timer(0, val1);
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val = mv_get_timer_control();
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val |= CPU_TIMER0_EN;
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if (period != 0)
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val |= CPU_TIMER0_AUTO;
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else
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val &= ~CPU_TIMER0_AUTO;
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mv_set_timer_control(val);
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return (0);
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}
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static int
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mv_timer_stop(struct eventtimer *et)
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{
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uint32_t val;
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val = mv_get_timer_control();
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val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
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mv_set_timer_control(val);
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return (0);
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}
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static void
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mv_setup_timers(void)
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{
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uint32_t val;
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mv_set_timer_rel(1, INITIAL_TIMECOUNTER);
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mv_set_timer(1, INITIAL_TIMECOUNTER);
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val = mv_get_timer_control();
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val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
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val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO;
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mv_set_timer_control(val);
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timers_initialized = 1;
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}
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