a45a86c8c7
The RISC-V PLIC (platform level interrupt controller) registers are divided up by "context", which is purposefully left ambiguous in the PLIC spec. Currently we assume each CPU number corresponds 1-to-1 with a context number, but that is not correct. Most existing PLIC implementations (such as SiFive's) have multiple contexts per-cpu. For example, a single CPU might have a context for machine mode interrupts and a context for supervisor mode interrupts. To complicate things further, FreeBSD renumbers the CPUs during boot, but the PLIC driver still assumes that CPU ID equals the RISC-V hart number, meaning interrupt enables/claims might be performed for the wrong context registers. To fix this, we must calculate each CPU's context number during attachment. This is done by reading the interrupt properties from the device tree, from which a mapping from context to RISC-V hart to CPU number can be created. Reviewed by: br MFC after: 3 weeks Differential Revision: https://reviews.freebsd.org/D21927 |
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