d9c9c81c08
rounddown2 tends to produce longer lines than the original code and when the code has a high indentation level it was not really advantageous to do the replacement. This tries to strike a balance between readability using the macros and flexibility of having the expressions, so not everything is converted.
545 lines
15 KiB
C
545 lines
15 KiB
C
/*-
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* Copyright (c) 2006 Olivier Houchard
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/types.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/pcb.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <vm/vm_extern.h>
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#include <arm/xscale/i8134x/i81342reg.h>
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#include <arm/xscale/i8134x/i81342var.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcib_private.h>
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#include "pcib_if.h"
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#include <dev/pci/pcireg.h>
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static pcib_read_config_t i81342_pci_read_config;
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static pcib_write_config_t i81342_pci_write_config;
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static int
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i81342_pci_probe(device_t dev)
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{
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struct i81342_pci_softc *sc;
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sc = device_get_softc(dev);
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if (device_get_unit(dev) == 0) {
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device_set_desc(dev, "i81342 PCI-X bus");
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sc->sc_is_atux = 1;
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} else {
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device_set_desc(dev, "i81342 PCIe bus");
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sc->sc_is_atux = 0;
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}
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return (0);
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}
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#define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008
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#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004
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static int
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i81342_pci_attach(device_t dev)
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{
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struct i81342_softc *parent_sc;
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struct i81342_pci_softc *sc;
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uint32_t memsize, memstart;
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uint32_t reg;
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int func;
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uint32_t busno;
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sc = device_get_softc(dev);
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parent_sc = device_get_softc(device_get_parent(dev));
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sc->sc_atu_sh = sc->sc_is_atux ? parent_sc->sc_atux_sh :
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parent_sc->sc_atue_sh;
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sc->sc_st = parent_sc->sc_st;
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if (bus_space_read_4(sc->sc_st, parent_sc->sc_sh, IOP34X_ESSTSR0)
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& IOP34X_INT_SEL_PCIX) {
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if (sc->sc_is_atux)
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func = 5;
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else
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func = 0;
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} else {
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if (sc->sc_is_atux)
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func = 0;
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else
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func = 5;
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}
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i81342_io_bs_init(&sc->sc_pciio, sc);
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i81342_mem_bs_init(&sc->sc_pcimem, sc);
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i81342_sdram_bounds(sc->sc_st, IOP34X_VADDR, &memstart, &memsize);
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if (sc->sc_is_atux) {
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reg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCSR);
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if (reg & ATUX_P_RSTOUT) {
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_PCSR,
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reg &~ ATUX_P_RSTOUT);
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DELAY(200);
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}
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}
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/* Setup the Inbound windows. */
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IABAR0, 0);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IAUBAR0, 0);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR0, 0);
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/* Set the mapping Physical address <=> PCI address */
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IABAR1,
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memstart | PCI_MAPREG_MEM_PREFETCHABLE_MASK |
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PCI_MAPREG_MEM_TYPE_64BIT);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IAUBAR1, 0);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR1,
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rounddown2(~(0xfff), memsize));
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR1, memstart);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IAUTVR1, 0);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IABAR2, 0);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IAUBAR2, 0);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR2, 0);
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/* Setup the Outbound IO Bar */
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if (sc->sc_is_atux)
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OIOBAR,
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(IOP34X_PCIX_OIOBAR >> 4) | func);
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else
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OIOBAR,
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(IOP34X_PCIE_OIOBAR >> 4) | func);
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/* Setup the Outbound windows */
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR0, 0);
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if (sc->sc_is_atux)
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR1,
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(IOP34X_PCIX_OMBAR >> 32) | (func << ATU_OUMBAR_FUNC) |
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ATU_OUMBAR_EN);
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else
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR1,
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(IOP34X_PCIE_OMBAR >> 32) | (func << ATU_OUMBAR_FUNC) |
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ATU_OUMBAR_EN);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMWTVR1, 0);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR2, 0);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR3, 0);
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/* Enable the outbound windows. */
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reg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_CR);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_CR,
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reg | ATU_CR_OUT_EN);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR,
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bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR) & ATUX_ISR_ERRMSK);
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/*
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* Enable bus mastering, memory access, SERR, and parity
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* checking on the ATU.
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*/
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if (sc->sc_is_atux) {
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busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
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busno = PCIXSR_BUSNO(busno);
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} else {
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busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCSR);
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busno = PCIE_BUSNO(busno);
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}
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reg = bus_space_read_2(sc->sc_st, sc->sc_atu_sh, ATU_CMD);
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reg |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_PERRESPEN |
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PCIM_CMD_SERRESPEN;
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bus_space_write_2(sc->sc_st, sc->sc_atu_sh, ATU_CMD, reg);
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sc->sc_busno = busno;
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/* Initialize memory and i/o rmans. */
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sc->sc_io_rman.rm_type = RMAN_ARRAY;
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sc->sc_io_rman.rm_descr = "I81342 PCI I/O Ports";
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if (rman_init(&sc->sc_io_rman) != 0 ||
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rman_manage_region(&sc->sc_io_rman,
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sc->sc_is_atux ? IOP34X_PCIX_OIOBAR_VADDR :
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IOP34X_PCIE_OIOBAR_VADDR,
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(sc->sc_is_atux ? IOP34X_PCIX_OIOBAR_VADDR :
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IOP34X_PCIE_OIOBAR_VADDR) + IOP34X_OIOBAR_SIZE) != 0) {
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panic("i81342_pci_probe: failed to set up I/O rman");
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}
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sc->sc_mem_rman.rm_type = RMAN_ARRAY;
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sc->sc_mem_rman.rm_descr = "I81342 PCI Memory";
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if (rman_init(&sc->sc_mem_rman) != 0 ||
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rman_manage_region(&sc->sc_mem_rman,
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0, 0xffffffff) != 0) {
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panic("i81342_pci_attach: failed to set up memory rman");
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}
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sc->sc_irq_rman.rm_type = RMAN_ARRAY;
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sc->sc_irq_rman.rm_descr = "i81342 PCI IRQs";
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if (sc->sc_is_atux) {
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if (rman_init(&sc->sc_irq_rman) != 0 ||
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rman_manage_region(&sc->sc_irq_rman, ICU_INT_XINT0,
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ICU_INT_XINT3) != 0)
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panic("i83142_pci_attach: failed to set up IRQ rman");
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} else {
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if (rman_init(&sc->sc_irq_rman) != 0 ||
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rman_manage_region(&sc->sc_irq_rman, ICU_INT_ATUE_MA,
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ICU_INT_ATUE_MD) != 0)
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panic("i81342_pci_attach: failed to set up IRQ rman");
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}
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR,
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bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR) & ATUX_ISR_ERRMSK);
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device_add_child(dev, "pci", -1);
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return (bus_generic_attach(dev));
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}
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static int
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i81342_pci_maxslots(device_t dev)
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{
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return (PCI_SLOTMAX);
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}
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static void
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i81342_pci_conf_setup(struct i81342_pci_softc *sc, int bus, int slot, int func,
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int reg, uint32_t *addr)
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{
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uint32_t busno;
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if (sc->sc_is_atux) {
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busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
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busno = PCIXSR_BUSNO(busno);
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} else {
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busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCSR);
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busno = PCIE_BUSNO(busno);
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}
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bus &= 0xff;
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slot &= 0x1f;
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func &= 0x7;
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if (sc->sc_is_atux) {
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if (busno == bus)
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*addr = (1 << (slot + 16)) | (slot << 11) |
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(func << 8) | reg;
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else
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*addr = (bus << 16) | (slot << 11) | (func << 11) |
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reg | 1;
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} else {
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*addr = (bus << 24) | (slot << 19) | (func << 16) | reg;
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if (bus != busno)
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*addr |= 1;
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}
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}
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static u_int32_t
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i81342_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
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u_int reg, int bytes)
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{
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struct i81342_pci_softc *sc = device_get_softc(dev);
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uint32_t addr;
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uint32_t ret = 0;
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uint32_t isr;
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int err = 0;
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vm_offset_t va;
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i81342_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, sc->sc_is_atux ?
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ATUX_OCCAR : ATUE_OCCAR, addr);
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if (sc->sc_is_atux)
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va = sc->sc_atu_sh + ATUX_OCCDR;
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else
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va = sc->sc_atu_sh + ATUE_OCCDR;
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switch (bytes) {
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case 1:
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err = badaddr_read((void*)(va + (reg & 3)), 1, &ret);
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break;
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case 2:
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err = badaddr_read((void*)(va + (reg & 3)), 2, &ret);
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break;
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case 4:
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err = badaddr_read((void *)(va) , 4, &ret);
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break;
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default:
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printf("i81342_read_config: invalid size %d\n", bytes);
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ret = -1;
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}
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if (err) {
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isr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR);
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if (sc->sc_is_atux)
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isr &= ATUX_ISR_ERRMSK;
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else
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isr &= ATUE_ISR_ERRMSK;
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR, isr);
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ret = -1;
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}
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return (ret);
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}
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static void
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i81342_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
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u_int reg, u_int32_t data, int bytes)
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{
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struct i81342_pci_softc *sc = device_get_softc(dev);
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uint32_t addr;
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vm_offset_t va;
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i81342_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, sc->sc_is_atux ?
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ATUX_OCCAR : ATUE_OCCAR, addr);
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va = sc->sc_is_atux ? ATUX_OCCDR : ATUE_OCCDR;
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switch (bytes) {
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case 1:
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bus_space_write_1(sc->sc_st, sc->sc_atu_sh, va + (reg & 3)
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, data);
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break;
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case 2:
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bus_space_write_2(sc->sc_st, sc->sc_atu_sh, va + (reg & 3)
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, data);
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break;
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case 4:
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, va, data);
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break;
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default:
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printf("i81342_pci_write_config: Invalid size : %d\n", bytes);
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}
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}
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static struct resource *
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i81342_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
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rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
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{
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struct i81342_pci_softc *sc = device_get_softc(bus);
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struct resource *rv;
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struct rman *rm;
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bus_space_tag_t bt = NULL;
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bus_space_handle_t bh = 0;
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switch (type) {
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case SYS_RES_IRQ:
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rm = &sc->sc_irq_rman;
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break;
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case SYS_RES_MEMORY:
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rm = &sc->sc_mem_rman;
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bt = &sc->sc_pcimem;
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bh = 0;
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break;
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case SYS_RES_IOPORT:
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rm = &sc->sc_io_rman;
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bt = &sc->sc_pciio;
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bh = sc->sc_is_atux ? IOP34X_PCIX_OIOBAR_VADDR :
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IOP34X_PCIE_OIOBAR_VADDR;
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start += bh;
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end += bh;
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break;
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default:
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return (NULL);
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}
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rv = rman_reserve_resource(rm, start, end, count, flags, child);
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if (rv == NULL)
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return (NULL);
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rman_set_rid(rv, *rid);
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if (type != SYS_RES_IRQ) {
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if (type == SYS_RES_MEMORY)
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bh += (rman_get_start(rv));
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rman_set_bustag(rv, bt);
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rman_set_bushandle(rv, bh);
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if (flags & RF_ACTIVE) {
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if (bus_activate_resource(child, type, *rid, rv)) {
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rman_release_resource(rv);
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return (NULL);
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}
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}
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}
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return (rv);
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return (NULL);
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}
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static int
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i81342_pci_activate_resource(device_t bus, device_t child, int type, int rid,
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struct resource *r)
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{
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bus_space_handle_t p;
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int error;
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if (type == SYS_RES_MEMORY) {
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error = bus_space_map(rman_get_bustag(r),
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rman_get_bushandle(r), rman_get_size(r), 0, &p);
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if (error)
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return (error);
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rman_set_bushandle(r, p);
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}
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return (rman_activate_resource(r));
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}
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static int
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i81342_pci_setup_intr(device_t dev, device_t child, struct resource *ires,
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int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
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void **cookiep)
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{
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return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags,
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filt, intr, arg, cookiep));
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}
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static int
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i81342_pci_teardown_intr(device_t dev, device_t child, struct resource *res,
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void *cookie)
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{
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return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
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}
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static int
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i81342_pci_route_interrupt(device_t pcib, device_t dev, int pin)
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{
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struct i81342_pci_softc *sc;
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int device;
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device = pci_get_slot(dev);
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sc = device_get_softc(pcib);
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/* XXX: Is board specific */
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if (sc->sc_is_atux) {
|
|
/* PCI-X */
|
|
switch(device) {
|
|
case 1:
|
|
switch (pin) {
|
|
case 1:
|
|
return (ICU_INT_XINT1);
|
|
case 2:
|
|
return (ICU_INT_XINT2);
|
|
case 3:
|
|
return (ICU_INT_XINT3);
|
|
case 4:
|
|
return (ICU_INT_XINT0);
|
|
default:
|
|
break;
|
|
}
|
|
case 2:
|
|
switch (pin) {
|
|
case 1:
|
|
return (ICU_INT_XINT2);
|
|
case 2:
|
|
return (ICU_INT_XINT3);
|
|
case 3:
|
|
return (ICU_INT_XINT2);
|
|
case 4:
|
|
return (ICU_INT_XINT3);
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
} else {
|
|
switch (pin) {
|
|
case 1:
|
|
return (ICU_INT_ATUE_MA);
|
|
case 2:
|
|
return (ICU_INT_ATUE_MB);
|
|
case 3:
|
|
return (ICU_INT_ATUE_MC);
|
|
case 4:
|
|
return (ICU_INT_ATUE_MD);
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
printf("Warning: couldn't map %s IRQ for device %d pin %d\n",
|
|
sc->sc_is_atux ? "PCI-X" : "PCIe", device, pin);
|
|
return (-1);
|
|
}
|
|
|
|
static int
|
|
i81342_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
|
|
{
|
|
struct i81342_pci_softc *sc = device_get_softc(dev);
|
|
switch (which) {
|
|
case PCIB_IVAR_DOMAIN:
|
|
*result = 0;
|
|
return (0);
|
|
case PCIB_IVAR_BUS:
|
|
*result = sc->sc_busno;
|
|
return (0);
|
|
|
|
}
|
|
return (ENOENT);
|
|
}
|
|
|
|
static int
|
|
i81342_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
|
|
{
|
|
struct i81342_pci_softc * sc = device_get_softc(dev);
|
|
|
|
switch (which) {
|
|
case PCIB_IVAR_DOMAIN:
|
|
return (EINVAL);
|
|
case PCIB_IVAR_BUS:
|
|
sc->sc_busno = result;
|
|
return (0);
|
|
}
|
|
return (ENOENT);
|
|
}
|
|
|
|
static device_method_t i81342_pci_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, i81342_pci_probe),
|
|
DEVMETHOD(device_attach, i81342_pci_attach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_read_ivar, i81342_read_ivar),
|
|
DEVMETHOD(bus_write_ivar, i81342_write_ivar),
|
|
DEVMETHOD(bus_alloc_resource, i81342_pci_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
|
|
DEVMETHOD(bus_activate_resource, i81342_pci_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
|
DEVMETHOD(bus_setup_intr, i81342_pci_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, i81342_pci_teardown_intr),
|
|
|
|
/* pcib interface */
|
|
DEVMETHOD(pcib_maxslots, i81342_pci_maxslots),
|
|
DEVMETHOD(pcib_read_config, i81342_pci_read_config),
|
|
DEVMETHOD(pcib_write_config, i81342_pci_write_config),
|
|
DEVMETHOD(pcib_route_interrupt, i81342_pci_route_interrupt),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t i81342_pci_driver = {
|
|
"pcib",
|
|
i81342_pci_methods,
|
|
sizeof(struct i81342_pci_softc),
|
|
};
|
|
|
|
static devclass_t i81342_pci_devclass;
|
|
|
|
DRIVER_MODULE(ipci, iq, i81342_pci_driver, i81342_pci_devclass, 0, 0);
|